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user4076341 said:we can set "io strength" to 2mA or 8mA, which one is better?
Which color is better - red or green? Depends upon other factors - not mentioned - by neither you nor I.
In general the less current you draw the cooler your circuits will run - and all things being equal - life will increase.
Another side of the coin (this unstated) is what is the requirement of your external circuit? It may require beyond 2 or 4mA to function properly - then your use of 8mA would be appropriate.
Be careful not to draw too much current from any one side of the 4-sided MCU. Back of the MCU manual may detail the maximum current draw across the whole MCU and - iirc - across any one side. Best to distribute the current flow as equally as possible throughout all 4 sides of the MCU.
Finally - MCU is never intended as "beast of burden!" It should be your intelligent control agent - process data, communicate & make decisions. Far better "power" chips, FETs and such are designed for high current - they should be so tasked over the MCU.
Hello user4076341,
Is the intent of using the circuit as an external pull up or as a fixed 3.3V connection?
Regards
Amit
this is an abnormal condition:
GPIO output with a serial resistor , but the outside maybe not used normally, it gives me a logic one signal which is 3.3V instead.
Although this is rare, we must ensure that nothing will be damaged, the signal is not considered anymore.
At the time: no signal or others is concerned, just MCU and resistor is cared, so how we set the strength to decrease the side-effect , there must be one be better.
Hi user4076341,
Actually, the complete circuit looks as follows:
GND--------[MCU internals]----[MCU GPIO]---------100 Ohm resistor----------------------pwr 3.3V
In that circuit, the power is dissipated by the two guys, the MCU and the resistor.
The resistor's power rating (1/10 W) does correspond to max current value about 33 mA.
I presume the main purpose of "drive strength" setting is to internally limit the current through the GPIO pin. So whatever the setting is (2mA or 8mA) the resistor is not a point of concern as that current values are well within the resistor's capability.
So your question boils down to "which value of the drive strength setting corresponds to minimal power dissipation by MCU". Calculation (or measurement) will provide you with the idea.
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regards,
Igor
Hello user4076341,
In that case I would suggest using a weaker serial resistor if the application permits.
Regards
Amit
Yes, the question is - which value corresponds to the minimal power dissipation by "MCU+resistor", measurement is a method, but the theory used here shall be cleared...
Some of our collegues recommend using the weak strength, but a ti engineer answered with using the strong one as the strength added, the abilily of anti-interference increase, confusing
Hello user4076341
It is a very application specific question. If you want to guard the input against noise spikes then the resistor needs to be stronger. On the other hand if is current sink that you want to guard against then a weaker resistance would be required.
As an example on I2C Bus, a stronger resistance would be good, but the current drain and the VOL may be higher than expected.
Regards
Amit
In fact i don't care about the abnormal condition with any noise, just the whole way current. So as all informations now get, it seems the 2mA may sink less current, which will be good to mcu and resistor.
Hello user4076341,
In which case I would suggest using a weaker resistor to limit the current through the IO when the abnormal condition occurs.
Regards
Amit
Hello Amit,
I think it better to make the usage clear: the design is a module, which can be used as binary input or output depend on the internal flash settings. Normally it's ok. But occasionally, the module configured as BO but plugged into a BI. When module output BO 0 and external give me BI 1, it leads to the above awkward status.
Normally the serial resistor is used to compensate for BI/BO signal overshoot, which is 33ohm or so instead. Since the awkward condition maybe met, the value is adjusted bigger to accormodate the sink current! At the abnormal status, the BI/BO signal is not cared anymore, we just care about if any hardware damage can occure, what we can do to decrease the side effect.
so, what's the choice of strength?
Hi,
I suggeset to read the chapter Electrical characteristics - GPIO strenghts are defined as "minimum", not maximum. I can confirm this is true, I had a case with strenght limit at 4 mA and the sink current was way higher, and the effect was the output low level rised more than specification.
The data sheet allows a maximum 70mA per pin per side (dependent), so in any case the best thing is to limit this current, not increase it. A maximum of 18 mA for standard output 1.5V is also specified - think is good to limit to this value - but depends also on what you intend to do with your modules - either to detect and correct this either to keep it as is, but both at safe levels.
The best thing of all would be to avoid such thing, using separate inputs/outputs, either to detect first the module type and after that make suitable configuration.
Petrei
As it can not be avoided, we're trying to get the problem solved: serial resistor formally 33ohm changed to 100 or even a little bigger, but no more since it may affect the normal BI/BO function.
Hello user4076341
Petrei's point is extremely important on the per side current I would suggest increasing the resistance to the point where Bi/BO function overshoot is not acceptable allowing to minimize the current being sinked into the pad/
Regards
Amit
Post has gone on so long - the "real" detail has only recently arrived.
It is (usually) not professional to allow two outputs - even if from different sources - to connect when each side may be unknown and may assume opposite output states! I'd bet that with better analysis your direct connect of 2 potential outputs (even resistor limited) could be avoided. The most reasonable justification I can identify is the requirement to, "change the direction of current flow" which requires each side (in turn) to source or sink current. And - we've done just that - but never by forcing the MCU to serve as "beast of burden." Instead - simple transistors - driven by the MCU - escape all of the potential damage which your present implementation creates. (You may choose to investigate classic "H Bridge" which manages selective/directional current flow.)
This "output to output" connection impacts (both) the MCU and external device - and (to me) demands that each side "know" when the other seeks to output - so that the other side may switch (quickly) into "pin_input" status. This may be achieved by the more classic use of 2 GPIO - connecting each side - with one serving as input - the other output. This enables "Command/Control" signalling.
Still - you've made no attempt to describe why 2 outputs must be connected - and I'd bet there exists a superior circuit implementation. Clarity of your (real) issue has been weak - so too (I'd bet) the need for such an abnormal, "output to output" connection...
Hi Amit,
That discussion (yet another one about GPIO output capability of the arm-based mcu) grows my suspicion that one of the following is true: I don't understand something or the amount of GPIO electrical parameters the spec documents does provide is not consistent with perceived purpose of the selectable output strength feature.
An industry-standard way to specify the load capability of a digital output terminal (MCU's GPIO pin or a pin of simple logic gate) is to specify the minimal value for the current the pin can provide to the load keeping the pin voltage below (for sink current) or above (for source current) certain limit. As for the maximal value, the cases vendor did specified it are extremely rare. So the capability ("strength") is specified as "of that value or better".
To estimate current in an external circuit driven by the output pin, sometimes it may be convenient to convert the pin's strength value to "internal resistance" (Ro) units. The lower Ro, the stronger the pin.
For the sink current case (under discussion), the Ro value can be calculated as Vol divided by the value of specified strength in mA units. Strictly speaking, the calculated Ro value is relevant just for that current but for rough estimation it can be assumed (educated guess) that the U(I) dependency is more-less linear.
Anyway that calculation gives only maximal Ro value because only the minimal current value is specified. As for the minimal Ro value, it can be assumed to be as low as zero. Unlikely the case but to be on the safe side.
Once the Ro value is found, the estimated current in the circuit can be calculated by division the voltage across the circuit by the total resistance value (Rload + Ro). In that way, min. and max. current values can be estimated (for max. and min. Ro values respectively). So if one is concerned about the max. current, he/she can estimate it for Ro=0.
The Tiva C MCUs has selectable GPIO strength feature and for each strength setting, the output current is specified by the data sheet in the usual way ("of that value or greater"). As such, for each strength setting, the minimal Ro value is of zero (for the reason mentioned above, as the max. current value is not specified).
The implication is the weak strength settings are, actually, not for internal current limitation (e.g. "2mA" setting does not limit the current to 2 mA). Hence, whatever the setting is, the designer anyway have to make sure the current in the circuit will not exceed the absolute max. value (calculate estimated current assuming Ro=0 and increase Rload value if necessary).
The question is what's real advantage comes with that feature?
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regards,
Igor
Hello Igor
The datasheet is in agreement with your statement. It is the minimum current sink/source that we specify in the data sheet. What limits the overall capability is the per side current for the device due to the stress that the power grid has to endure for the setting the current in a particular setting of strength.
Regards
Amit
Just to emphasize - employing (any) MCU as "beast of burden" is not ideal. Other devices exist - which are far better equipped/designed - for that (current handling) purpose.
Having past worked for (another) major, semi-firm I can report that easily 90% of MCU field failures resulted from users "bumping against - or dynamically exceeding" those limits which both the MCU manual & vendor's Amit have noted here. Even worse - some percentage of these failures resulted even when user had, "complied with the MCU's written spec - yet had "approached" the limit!" (I cannot recall that exact number - this may be explained by device aging - or lot/process variation - or...) Point remains - not "best practice" to fire cannon ball w/small pistol.
That "per side" limitation proves especially deadly - and if the MCU operates w/in a high ambient - and at, "full throttle" the MCU's internal power paths are often, "over-challenged."
It's normal these days for designs to change - likely be expanded - and, "adding just one more Led - or other current demand to the MCU - can't really hurt!" Except that it can - and does! Too often that "per side" rule is forgotten (or violated) during the "heat of design expansion" - with unwelcome results...
Cost/size "penalty" of SOT FET is unlikely to burden most all here - and greatly assists the MCU's, "life expectancy."
That's a good point. There are some MCU types with a rudimentary core and outstanding output current capability. But advantages always comes at the cost so for the type under discussion this is a really good point.
Just recalled in mid 70's I was working for a design house that had only one customer and there was a customer-enforced design rule "For each part, actual load shall never exceed 30% of the absolute max. rating.
The things are getting more complex. For a Microchip's MCU the data sheet can be just of 20 pages, for a 68k-based MCU the data sheet can be of 400 pages, for a Tiva MCU it's of more than 1500 pages and for OMAP4 it's of more than 5k pages. That's a huge numbers (so the amount of information to digest by user timely). No wonder each topic in the data sheet has only bare minimum coverage.
The GPIO facility is widely used in embedded control applications (target area for Tiva) and on early project stage clear understanding for the GPIO pin's capabilities cannot be underestimated.
In the Tiva MCUs, allowed current for each particular GPIO pin has a multi-dimensional limiting vector (per pin, per side, etc.) and the selectable drive strength feature just adds one more dimension.
Meanwhile the related information in the data sheet is so optimized that just one overlooked string can result in less than complete understanding. That, in turn, can eventually result in an unintentionally over-stressed part (unless the design flaw is identified before production run).
Because of apparent complexity and importance of that matter, I think it'll make sense for TI to provide better coverage. Somewhere in application notes. Btw, I've checked the system design guidelines for Tiva. Each the document contains just single page with the GPIO-related recommendations. Definitely not enough (compare it with the app note that discusses the 5V-tolerant GPIO for tm4C123, spma053). Provision of related nice-to-have information will also help users. This support case is a perfect example: http://www.cypress.com/?app=forum&id=167&rID=72946
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regards,
Igor
As sayed before, the module designed with configuring BI/BO is pluggable with other boards is as follows:
since the module is pluggable, we can't guarantee all persons in job sites doing things correctly, so error may happen. We hope when error happens, no damage will occur, no doubt that function is wrong, so everything will be checked and corrected. Design must ensure that no damage at the coures even it not last long.
Discussions above mentioned on current per side shall be considered certainly, we just distribute the used GPIO to different side. Now we're trying to see if we can do more like setting different strength.
Igor Uspensky1 said:...Tiva MCUs, allowed current for each particular GPIO pin has a multi-dimensional limiting vector (per pin, per side, etc.)
and
Igor Uspensky1 said:...related information in the data sheet is so optimized that just one overlooked string can result in less than complete understanding.
Not that such (agreement) makes either of us right - but my tech team (et moi) applaud poster's extremely effective word-play - in highlighting potential dangers when one, "Takes this baby (MCU) to the MAX!" (my group works @ the nexus of tech/legal/finance - thus words - their composition & fit - are crucial - must be properly crafted & cadenced to prevent misunderstanding/dispute/cost-over-run/lawsuit...)
Quite simply - "Risk-Reward" (properly) dictates that one NOT try to squeeze, "every drop of power" from the MCU!" (especially when alternative - designed to purpose devices (FETs) - are inexpensive & readily available!) To be clear -this is no knock upon this vendor - nor these MCUs - this is (but for special exceptions - as poster noted) a, "near universal" caution.
The op's writing remains uncertain/unclear - I see no advantage to the most recently arrived, "circuit incarnation." As this drawing shows - the MCU should (only) respond to a signal input - thus be placed in GPIO as Input mode - thus any/all "MCU Output current settings are irrelevant." (i.e. they do not "play" when MCU is an input)
Ignored thus far - use of SOT FET - is a far more appropriate current source/sink than most any MCU's GPIO.
My group has long fought against (this & other) vendors' efforts to present MCU as, "Kitchen Sink!" (i.e. do everything - even those things for which the MCU's "packed" circuit routings become (often) over-challenged...)
Seems the intention is to get a fool-proof design (no software error can cause to hw damage). Other than that, the diagram shows that the input voltage is coming from outside world (external to the board). TVS diodes can help to make the design also a bullet-proof :)
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regards,
Igor