TMS570LS4357 "transaction ECC" and "transaction parity" test.

Hi Libo,

  I'm terribly sorry that this post was assigned to me for two weeks and I totally missed it. Please find my answers inline.

Question 1: Is Transaction ECC tested by the CPU interconnect self test? If not, how to test this feature?

Charles>> There are two ECC blocks inside the CPU interconnect. But these two ECC blocks are not covered by the self test. Let me explain a bit. To make it simple for you to understand I will just say that there is the inner CPU interconnect which is further wrapped around by additional logic. This outer wrapper includes also the two ECC blocks. However, the selftest is only done on the inner CPU interconnect. The logic at the wrapper side is not subject to the interconnect selftest. You can first write mismatched data and ECC pair to the L2SRAM first and then use the DMA PortA to read from the test address. It should result in ECC error that you can observe in the ESM. 

Question 2: I have started the transaction parity test by setting SCMCNTRL to 0x0A050505 as described in section 3.3.1 in the TRM. After the store instruction, I see that 4 flags in ESM are set: ESM1.52, ESM1.70, ESM2.7, ESM2.17. Why is ESM1.53 (Global parity error) not set?

Charles>> As mentioned, the selftest does not involve the parity and ECC diagnostic that are present in the wrapper logic around the interconnect and therefore the global parity error is not asserted.

Question 3: Extract from TRM section 3.3.1:

"The interconnect also output an inverted polarity for output control and address signals. Thus, master and slave IP connected to interconnect could potentially generate parity error as well. ... You should clear all parity error status bits residing in master IP, slave IP, or interconnect status registers."

How can I make sure that all master and slave status registers are cleared? Is it enough to check the status registers of the masters and slaves which are shown in the ESM flags? For example, ESM1.52 implies that I shall clear the status register SDC_STATUS, ESM1.70 ---> DMA, ESM2.7 --> L2RAMW, and ESM2.17 --> Flash. Is there any IPs which may store parity status but is not reflected in ESM flags? Usually a new error or error address can't be stored/flagged if an old error is not cleared. Therefore I must ensure all flags triggered by the transaction parity self test are cleared. That's the reason I ask this question.

Charles>> Yes, please clear these parity error flags in DMA, L2FMC and L2RAMW. There are no other modules on the CPU interconnect that will set parity error flags.