N2HET TMS570

Hi,

1. Is the limit of 160 instructions stated per N2HET, i.e 160 instructions available for N2HET1 and 160 instructions available for N2HET2?

>> Yes, each N2HET module has a 160-word memory associated with it.

2. Are there any significant differences between the N2HET1 and N2HET2 modules except for amount of dedicated pins?

>> The two N2HET modules are identical. Any differences are in the connections to these modules, e.g. terminals assigned, event trigger capability, dual-clock-comparator connections, etc., which are documented in the datasheet.

3. I have seen some encoder example code here on the forum. Are there any restrictions of how to use the HET pins? Can I choose any two of the HET pins to cooperate as an encoder?

>> The encoder example using N2HET uses three pins, one each for A, B and the Index signal. Any three N2HET pins can be used for either of these functions. You can choose them based on the pinout and availability.

4. Is the data field for each instruction accessable by an application running on the TMS570? Or is it so that the data has to be transferred to some specific registers in order to be accessable by an application?

>> The N2HET RAM includes the program field, control field and the data field. The application can directly write to the data field directly as this is memory-mapped. This write would be completely asynchronous to the N2HET module operation, so you need to be careful to account for any implications. A safer method would to use a MOV32 instruction for data field updates. Consider the example below:

L00   CNT   {next = L01, reg=A, max= 4 }

       	; count: increment immediate data field (counter) of this
		; instruction and write new value to reg_A
       	; if (counter == max) 
       	; {set Z=1; reset immediate data field and reg_A to zero}

L01   ECMP  {next=L00, cond_addr=L00, en_pin_action=ON, pin=CC1, 
             action=PULSELO, reg=A, irq=OFF,  data= 2, hr_data= 80}

       	; if (reg_A == data_field) { clear   CC1 }
       	; if (      Z==1         ) { set CC1 }
       	; goto L00

The CPU can directly write to the data field of the ECMP instruction (ECMP_DF). This could cause an abnormal pulse width in the output PWM as shown below, depending on the timing of the CPU write to the ECMP_DF.

As you can see, the CPU write to the ECMP_DF causes the compare match to n1 in the current counter cycle to be missed. This causes the wider pulse on the PWM output, which is undesirable.

The safer method is:

L00  CNT   {  reg=A,   max= 3 }

       	; count: increment immediate data field (counter) of this
		; instruction and write new value to reg_A
       	; if (counter == max) 
       	; {set Z=1; reset immediate data field and reg_A to zero}

L01  MOV32 { remote = L02, type = IMTOREG&REM, z_cond = ON, reg = NONE, 
                                   data = 2, hr_data = 80 }
       	; if Z==1 copy data immediate data field to remote ECMP_DF

L02  ECMP  {next = L00, cond_addr = L00, en_pin_action=ON, pin=CC0, 
             action=PULSELO, reg=A, data= 2, hr_data= 80}

       	; if (reg_A == data_field) { clear CC0 }
       	; if (      Z==1         ) { set   CC0 }
       	; goto L00

In this case, the CPU updates the duty cycle by writing to the data field of the MOV32 instruction. The MOV32 instruction moves the contents of its data field to the data field of the ECMP instruction only once the counter rolls over to zero (Z = 1). This avoids generation of any "abnormal" pulse widths in the output PWM.

Regards, Sunil