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BASEPRI on TM4C question

Thomas Roell
Prodigy 20 points

I got a curious question, perhaps somebody can help me out.

If I write a 0x00 to BASEPRI, then all interrupts are unmasked. If I write a 0x80 all interrupts that have a PRIO of less or equal to 0x80 are masked. So far so good. The TM4C really implements only 3 bits of priority, so the LSBs should not matter.

But what happens if I write a 0x01 to BASEPRI ? Will that mask ALL interrupts that have a PRIO of less or equal to 0x01, which means all interrupts on a TM4C ? Or does it do the same as writing a 0x00 ?

 

- Thomas

  • 0
    Guru 26105 points

    Hi,

    In Tiva only the three upper bits are active, the rest, bits 4..0 are reserved and should not be touched (even you cannot write since are declared as read-only).

    The user manual of your micro has a description of this register.

    Petrei

  • 0 in reply to Petrei
    Prodigy 20 points

    It says for NVIC. But BASEPRI is a CPU Core register. So I was wondering whether this makes a difference.

    But you are right, the TM4C manual says that only 3 bits are implemented for BASEPRI as well.

    - Thomas