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RM48 - Issues using ELF function from flash to SDRAM



Hello,

My firmware copies some flash data into the SDRAM (using ELF functions __iar_sb) and then cast that information into a structure. However when I cast it I can see how the information is shifted.


So I put in breakpoint where the data should be copied and I stepping through the code the data is passed from Flash to SDRAM correctly, however, when running without code this is not being done properly (the values in the structure are shifted).

Is this a known problem with the SDRAM/Processor?


The instruction that is passing the value into the SDRAM is a STR function.

Regards,

  • Hector,

    It sounds like it is a software problem.

    Can you copy the flash data to internal RAM, cast as a struct, and successfully execute?

  • Hi Anthony,

    Yes I can, but the size is reduced.

    I also can do it in the SDRAM as long as the size of the data is not big, when I try to manage big data structures is when I have the problem.

    What makes me doubt is the fact that a simple log breakpoint in the instruction makes the structure show the correct data, however when I run the code without the breakpoint the data is wrong..

    with breakpoint

    field 1 = data 1

    field 2 = data 2

    field 3 = data 3

    without breakpoint

    field 1 = data 2

    field 2 = (empty)

    field 3 = data 3

    Thanks for your quick reply,

  • Hector,

    Sounds strange - at least I'm having a hard time understanding how this might happen and why the breakpoint would make a difference.

    Would it be possible to get more information.
    For example what are the addresses and data values involved in both examples.

    Also where in memory is the code that you are executing and putting the breakpoint on loaded & executing from?

    Best Regards,
    Anthony

  • Hi Anthony,

    For company policy I can't post any code but I will try to show you as much information as I can.

    the structure is similar to

    struct
    {
      u8 * version;
      char * name;
      ...
    }

    the address of the instruction is in

    0x103118

    the instruction is

    STR R4,  [R11, #-0xd]

    R4has the value that should put in the version (2),

    R11 -0xd  has the address where that value is stored (0x80411458)

    A couple of more instruction ahead I have the following instruction:

    0x103124

    STR R4,  [R11, #-0x9]

    R4 has the pointer to the string containing the name (0x80411291)

    R11-0x9 has the address where the string needs to be stored (0x80411465)

    Thats what I can see where i put the breakpoint.

    However, without the breakpoint what happens is that puts the string containing the name (0x80411291) in the field of the version (0x80411458).

    I dont need to put a breakpoint just in the instruction, just with a breakpoint in the near instructions the code works correctly.

    As I see is not a common failure but I tried to increment the SDRAM-EMIF to the maximum timing and still didnt work.

    Thanks,

    EDIT: fixed confussing mistakes

  • Hector,

    Ok, so the instructions are executing from internal flash -- that helps take out some variables.

    I'm confused with the struct declaration versus the instructions you are describing.

    In:

    struct
    {
      u8 * version;
      char * name;
      ...
    }

    both version and name are pointers and would be 32-bit values on this processor.
    that matches the fact that you are reporting a STR instruction (32-bit write) is used to write to them.

    But I'm having a hard time understanding why these members are not adjacent
    (one had address 0x80411458 but the other 0x80411465?) I would expect
    0x80411458 and 0x8041145C. And the way that you are describing 'name' as a string makes me think that you
    might be expecting the entire string to be stored inside the struct rather than a pointer to this string somewhere else
    in memory.

    What timing are you using for the SDRAM / EMIF?

    Also have you checked the pinmux to make sure all the EMIF pins are configured as EMIF? I think some default to trace pins,
    in which case if you don't have these configured something like a breakpoint could perturb the SDRAM functionality (by putting different
    trace data.. depending on whether a breakpoint is set or not... on the SDRAM lines instead of EMIF signals.)

  • Hi Anthony,

    The code is part of a third party software package.

    It has been tested in other Cortex M4/R4 devices and works correctly in the internal RAM.

    For copyright reasons I can't post the code online so if you know any other way that doesn't compromise the confidentiality I would be agree with it.

    Thanks,

  • Hector,

    You can email it to me directly.

    Most of the other Cortex devices on the market are little endian.  So this could be an issue of endian if you are using a TMS570 part # which is BE32. 

  • Hi Anthony,


    The conversation continues by email.

    Thanks,