Low Power Mode Examples?

Hi Josiah,

Yes this is an area where we could use more clarity on the procedure and an example.  I'm not aware of any good example and I've asked a lot of questions about this part of the TRM myself.   Will try to at least give some answers though:

Josiah Yeagley31 said:

• Program the flash banks and flash pump fall-back modes to be “sleep”. The flash pump transitions from active to sleep mode only after all the flash banks have switched from active to sleep mode. The flash banks start switching from active to sleep mode only after the bank are not accessed for at least a duration defined by the Active Grace Period (AGP) parameter configured for the banks. See Chapter 5 for more details.

I'm not sure I'd sweat this one too much since there is an errata (B066) see comments on step 4 below.

Josiah Yeagley31 said:

2. There are these 3 registers CSDIS, CSDISSET and CSDISCLR. I can set bits in these registers to disable the various clock sources. Which ones i set in which registers is a little unclear to me.... bit 1 corrsiponds to clock source 1 but in which register?

Clock Sources are the clock 'producers' if you will.  The Domains are the 'consumers'.

Table 2-3 in the TRM lists the clock sources by number, and the information is repeated in Table 2-28 specific to the bit # in the CSDIS register.    There would be 2 reasons to have set and clear versions of the register.  The first is to make it easy to set and clear a bit without doing a read-modify-write so that if you have multiple tasks manipulating the same register, they wouldn't necessarily step on each other.   That is why we have these for the GIO registers.   In this case, the reason may be that the CSDIS shows the actual status of the clock source but CSDISSET/CLR are your requests.  For example there is a note "Note: After a new clock source disable bit is set via the CSDISSET register, the new status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET
register (offset 34h) and the CSDISCLR register (offset 38h)."  that leads me to think the request may not immediately be acted on and so you might for example request that a clock source turn off but for various reasons it may not do so immediately.    And section 2.2.1.1 hints at this as well "The clock source is only disabled once there is no active clock domain that is using that clock source. Also, see Chapter 10 for more information on enabling/disabling the oscillator and PLL.."

This is an example of what I meant by gotchas before.  The information in the TRM chapter really hasn't been digested into an example 'procedure' that you can simply follow.

Josiah Yeagley31 said:

Apparently the 3 registers CDDIS, CDDISSET and CDDISCLR are also used to disable clock domains??? Now i'm confused because it sais bit 1 ALSO disables the clock domain for a clock domain... 0.o

Yes, but these are different registers.    CSDIS versus CDDIS.    I constantly get these confused myself because the names are so similar.

Josiah Yeagley31 said:

4. I think i have to set CDDIS bit 0 to 1 and this should do it for me.... 

Well you need to have the WFI instruction in your code.  And there is an errata that applies to this step.

(Device#B066 HCLK Stops Prematurely when Executing from Flash).  I think the GIST of this errata is that the grace periods don't work (from step 1) so you have to put your WFI immediately following the CDDIS write or else the CPU might execute junk.

One thing I should point out is that the flash process in which we build the part is 65nm and the leakage is considerable at high temp.   So turning off all these clocks you might still be over 100mA if your power is just on and the junction temp is high.   A lot of customers who operate in this range find it necessary to switch off power completely if they are running from a battery...

There is some good information in the footnotes of the table "Power Consumption Over Recommended Operating Conditions" which is table 3-5 in SPNS185A  {RM46L852 datasheet}.   If you look at this formula you can get an idea of what you can control with frequency (the low power modes basically drive frequency to 0 if you shut everything off) and the contribution of leakage which is just temperature and voltage dependent.   This might help you decide if it's worth going through the trouble of entering sleep.

Regarding wakeup,  Table 2-5 gives some examples of the wakeup options.   These depend on whether or not you have left any clocks running.   In the case of Sleep where there are no clocks running, you are limited to level sensitive input pins generating interrupts.

Also I don't see this in the 4 step procedure but it probably merits understanding 2.2.3.3 .. selecting clock source upon wakeup.  Table 2.5 Typical Low Power Modes makes a suggestion for the clock source upon wakeup.

Since this is determined by the GHVWAKE field, it can probably be setup when you initially write to GHVSRC during the first power up and left alone after that.    Maybe that's why it's not listed in the 4 step procedure ... because it's assumed you already thought of this and handled it in the startup code.

Definitely would like to know what you find as there are lots of other people who could benefit.

Josiah,

Let me try to explain the sequence based on the description from the TRM itself.

1. Program the flash banks and flash pump fall-back modes to be “sleep”. The flash pump transitions from active to sleep mode only after all the flash banks have switched from active to sleep mode. The flash banks start switching from active to sleep mode only after the bank are not accessed for at least a duration defined by the Active Grace Period (AGP) parameter configured for the banks. See Chapter 5 for more details.

>> The flash banks/pump are one of the key "gates" to be able to turn the system clock (HCLK) domain off. The flash interface module "allows" the HCLK domain to be turned off only after the flash banks and pump have entered their own "sleep" state. As stated in the above paragraph, the "active grace period" counter starts counting once it detects no flash bank accesses. This is possible only once the CPU clock domain (GCLK) is disabled. So the first step in putting the part into any low-power mode is to disable the GCLK clock domain. Configuring the flash bank and pump "fall back" modes to "sleep" only indicates that they need to enter their individual sleep modes once their AGP counters expire. The actual entry to sleep mode will be initiated once the CPU clock domain gets disabled.

1. Disable the clock sources that are not required to be kept active. A clock source does not get disabled until all clock domains using that clock source are disabled first, or are configured to use an alternate clock source.

>> The clock sources that need to be disabled depends on the actual low-power mode that you plan to enter. We have pre-defined the three LPMs (doze, snooze and sleep) depending on which clock sources you could choose to keep active through the low-power state. For example, the main oscillator could be kept active while all other clock sources (PLLs, LPO) could be disabled. This is the doze mode, and allows for a faster wake-up.

>> A clock source can be commanded to be disabled by writing to either the Clock Source Disable (CSDIS) register or setting the correct bit(s) in the CSDISSET register (avoids read-modify-write operation). As part of the safety requirements to be fulfilled, a clock source does not really get disabled until all clock domains using this clock source are either switched over to another clock source or are themselves disabled first. For example, let's say you want to enter doze mode. So you will set all bits in the CSDISSET register except for bit 0 (for the main oscillator). Now suppose that the GHVSRC register has been configured such that the GCLK/HCLK/VCLK domains are sourced by PLL1. In this case, even if you set the bit 1 of the CSDISSET register (corresponds to PLL1), PLL1 will not get disabled until the GCL/HCLK/VCLK domains are either switched over to another clock source, or are disabled first.

1. Disable the clock domains that are not required to be kept active. A clock domain does not get disabled until all modules using that clock domain “give their permission” for that clock domain to be turned off.

>> This is done by configuring the Clock Domain Disable (CDDIS) register or setting the correct bit(s) in the CDDISSET register (again, to avoid a read-modify-write operation). As explained earlier with respect to the flash interface module holding HCLK active, there are "gates" to be closed before any clock domain can be disabled. Configuring the CDDIS or CDDISSET register only indicates which clock domains need to be disabled once their disabling conditions are met.

1. Idle the Cortex-R4F core. The ARM Cortex-R4F CPU has internal power management logic, and requires a dedicated instruction to be used in order to enter a low power mode. This is the Wait For Interrupt (WFI) instruction. When a WFI instruction is executed, the Cortex-R4F core flushes its pipeline, flushes all write buffers, and completes all pending bus transactions. At this time the core indicates to the system that the clock to the core can be stopped. This indication is used by the Global Clock Module (GCM) to turn off the CPU clock domain (GCLK) if the CDDIS register bit 0 is set.

>> This is the main "entry point" into the desired low-power mode. As discussed earlier, this steps allows the CPU clock domain (GCLK) to be disabled. This allows the flash interface module to count down the AGP for the bank/pump and put these macros to sleep. This, in turn, allows HCLK domain (and VCLKx) to be disabled. If you want to enter a low-power mode wherein a clock source is kept active (doze/snooze), then usually you will configure the RTICLK domain to be sourced from this active clock source. In this case, the RTICLK domain is not disabled, but switched over to use the main oscillator or LPO as its source. This allows you to periodically wake up the part using main oscillator + RTI as the time base generator.

>> Once all clock domains except RTICLK are disabled, all the commanded clock sources will also get disabled (except for the one that is clocking the RTI), and the part is now considered to be in a low-power mode.

My guesses on how to do these things are as follows:

1. I read and mostly understand what its telling me to do but i don't see how to do it exactly. When i go to chapter 5 I see there is are PSLEEP bits (16-26) in register FPAC1. Do i set ALL of these to 1? 
   • PSLEEP is a counter that is used during power-up or wake-up for the flash pump. This counter is clocked at a frequency of HCLK/2. If you choose to enter doze mode, it is also better to choose the main oscillator to be the clock source for G/H/VCLK domains upon wake-up (this is done via the GHVLPM field of the GHVSRC register). The default (reset) value of the counter is chosen such that there is sufficient time allowed for the pump to transition from its sleep state to active state given an HCLK frequency of 20MHz (max main oscillator frequency supported). You can choose to increase this value if you so desire, or leave it at the default setting.
2. There are these 3 registers CSDIS, CSDISSET and CSDISCLR. I can set bits in these registers to disable the various clock sources. Which ones i set in which registers is a little unclear to me.... bit 1 corrsiponds to clock source 1 but in which register?
   • You can write directly to the CSDIS register. In this case there is a likelihood to accidentally disable a clock source you wanted to keep active. It is safer to just set the bit(s) for the exact clock source you want to disable by writing to the CSDISSET register.
3. Apparently the 3 registers CDDIS, CDDISSET and CDDISCLR are also used to disable clock domains??? Now i'm confused because it says bit 1 ALSO disables the clock domain for a clock domain...
   • Hope the distinction between a clock source and a clock domain is clearer now. The CDDIS or CDDISSET registers are used to disable specific clock domains.
4. I think i have to set CDDIS bit 0 to 1 and this should do it for me.... 
   • Setting this bit commands the GCLK domain to be disabled. The actual domain will only be disabled once the CPU executes the "WFI" instruction.

Hope this helps.

Regards, Sunil