Hello,
A customer is writing a bootload wiht TIMRE interrupt, they want to add another timer interrupt, how to modify the NVIC-TABLE offset.
I modify it as below, find can't work normal. Do we have an example code about it?
export __Vectors
__Vectors
dcd g_pulStack + (_STACK_SIZE * 4) ; Offset 00: Initial stack pointer
dcd Reset_Handler ; Offset 04: Reset handler
dcd NmiSR ; Offset 08: NMI handler
dcd FaultISR ; Offset 0C: Hard fault handler
dcd IntDefaultHandler ; Offset 10: MPU fault handler
dcd IntDefaultHandler ; Offset 14: Bus fault handler
dcd IntDefaultHandler ; Offset 18: Usage fault handler
dcd 0 ; Offset 1C: Reserved
dcd 0 ; Offset 20: Reserved
dcd 0 ; Offset 24: Reserved
dcd 0 ; Offset 28: Reserved
dcd UpdateHandler ; Offset 2C: SVCall handler
dcd IntDefaultHandler ; Offset 30: Debug monitor handler
dcd 0 ; Offset 34: Reserved
dcd IntDefaultHandler ; Offset 38: PendSV handler
if :def:_ENET_ENABLE_UPDATE
import SysTickIntHandler
dcd SysTickIntHandler ; Offset 3C: SysTick handler
else
dcd IntDefaultHandler ; Offset 3C: SysTick handler
endif
if :def:_UART_ENABLE_UPDATE :land: :def:_UART_AUTOBAUD
import GPIOIntHandler
dcd GPIOIntHandler ; Offset 40: GPIO port A handler
else
dcd IntDefaultHandler ; Offset 40: GPIO port A handler
endif
if :def:_USB_ENABLE_UPDATE :lor: \
(_APP_START_ADDRESS != _VTABLE_START_ADDRESS)
dcd IntDefaultHandler ; Offset 44: GPIO Port B
dcd IntDefaultHandler ; Offset 48: GPIO Port C
dcd IntDefaultHandler ; Offset 4C: GPIO Port D
dcd IntDefaultHandler ; Offset 50: GPIO Port E
if :def:_UART_ENABLE_UPDATE
import UART0_ISR
dcd UART0_ISR
else
dcd IntDefaultHandler ; Offset 54: UART0 Rx and Tx
endif
dcd IntDefaultHandler ; Offset 58: UART1 Rx and Tx
dcd IntDefaultHandler ; Offset 5C: SSI0 Rx and Tx
dcd IntDefaultHandler ; Offset 60: I2C0 Master and Slave
dcd IntDefaultHandler ; Offset 64: PWM Fault
dcd IntDefaultHandler ; Offset 68: PWM Generator 0
dcd IntDefaultHandler ; Offset 6C: PWM Generator 1
dcd IntDefaultHandler ; Offset 70: PWM Generator 2
dcd IntDefaultHandler ; Offset 74: Quadrature Encoder 0
dcd IntDefaultHandler ; Offset 78: ADC Sequence 0
dcd IntDefaultHandler ; Offset 7C: ADC Sequence 1
dcd IntDefaultHandler ; Offset 80: ADC Sequence 2
dcd IntDefaultHandler ; Offset 84: ADC Sequence 3
dcd IntDefaultHandler ; Offset 88: Watchdog timer
if :def:_UART_ENABLE_UPDATE
import ISR_Timer0_32
dcd ISR_Timer0_32
else
dcd IntDefaultHandler ; Offset 8C: Timer 0 subtimer A
endif
dcd IntDefaultHandler ; Offset 90: Timer 0 subtimer B
dcd IntDefaultHandler ; Offset 94: Timer 1 subtimer A
dcd IntDefaultHandler ; Offset 98: Timer 1 subtimer B
dcd IntDefaultHandler ; Offset 9C: Timer 2 subtimer A
dcd IntDefaultHandler ; Offset A0: Timer 2 subtimer B
dcd IntDefaultHandler ; Offset A4: Analog Comparator 0
dcd IntDefaultHandler ; Offset A8: Analog Comparator 1
dcd IntDefaultHandler ; Offset AC: Analog Comparator 2
dcd IntDefaultHandler ; Offset B0: System Control
dcd IntDefaultHandler ; Offset B4: FLASH Control
endif
if :def:_USB_ENABLE_UPDATE :lor: \
(_APP_START_ADDRESS != _VTABLE_START_ADDRESS)
dcd IntDefaultHandler ; Offset B8: GPIO Port F
dcd IntDefaultHandler ; Offset BC: GPIO Port G
dcd IntDefaultHandler ; Offset C0: GPIO Port H
dcd IntDefaultHandler ; Offset C4: UART2 Rx and Tx
dcd IntDefaultHandler ; Offset C8: SSI1 Rx and Tx
dcd IntDefaultHandler ; Offset CC: Timer 3 subtimer A
dcd IntDefaultHandler ; Offset D0: Timer 3 subtimer B
dcd IntDefaultHandler ; Offset D4: I2C1 Master and Slave
dcd IntDefaultHandler ; Offset D8: Quadrature Encoder 1
dcd IntDefaultHandler ; Offset DC: CAN0
dcd IntDefaultHandler ; Offset E0: CAN1
dcd IntDefaultHandler ; Offset E4: CAN2
dcd IntDefaultHandler ; Offset E8: Ethernet
dcd IntDefaultHandler ; Offset EC: Hibernation module
if :def: _USB_ENABLE_UPDATE
import USB0DeviceIntHandler
dcd USB0DeviceIntHandler ; Offset F0: USB 0 Controller
else
dcd IntDefaultHandler ; Offset F0: USB 0 Controller
endif
endif
