According to the Data sheet, TXFF goes low or high when:
'0' The transmitter is not full.
'1' If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
However, I am going through a work book, and the program seems to say something different but it still works (and yes I am using the exact same model; I have tested it myself). In the code I am working with, the FIFO is disabled. What gets me confused is that the bottom while loop executes when TXFF is '1', but this means the holding register is full according to the data sheet -- and the data register is then loaded. But this seems counter intuitive because it seems like the data register should only be loaded when the holding register is empty. But to me it seems like the code is not working this way. And of course this code works. That means I am not seeing something correctly. Here is the small piece of code:
while(( UART0-> FR & 0x20) != 0); /* wait until Tx buffer not full */
UART0-> DR = c; /* before giving it another byte */ }
Any suggestions would help! Thank you.
