why the slave cannot receive data in mibspi mode

I get the example from
http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/311317
It's Praveen Kumar ravichandran who give the example.

Hi,

Do you also have SCS[1] through SCS[5] set as SPI pins? (This is the default.)

If you do then they will need to be pulled up or else your slave will not be selected.
But the easiest thing to do would be to set these pins as GIO instead of SPI, so that they are don't care from the SPI point of view.
Also - I assume you left CSDEF as a value of 0xFF otherwise let me know.

How about the ENA pin? Did you configure this for SPI or GIO? I don't *think* this would be a problem if you see the master transmitting though.

Hopefully it is just the pin settings for the chip select. But if not:

- What signals have you wired from board to board, and how do you have them connected?

- What do the RAM locations in the MibSPI RAM say on the master and slave both before and after the transfer (transfer from master).
It would be good to know if any status changes in the slave's RAM to indicated that it saw something from the master. (even if it wasn't received correctly).

Hi

I am in conference all day, so I have to reply at night. 

Floooeing your advice, I set the SCS[1] through SCS[5] as GIO, and I also set the ENA as GIO. I leave the CSDEF as a value of 0xFF. but it still cannot work

To more easy, I change the MIBSPI1 to the PIBSPI5, as the MIBSPI5 only have SCS0 and ENA ,not like the MIBSPI1 which also have SCS1  SCS2 and so on. But it also cannot work . I AM ALMOST CRAZY.

I transfer a array ,as following

I use the oscilloscope to watch the signal of the master

the CLK

the SCS0      

in my opinion, the SCS0 should be low always, why this signal have pulse. 

the MOSI

Also I do a experiment, I set two piece of TMS570 which are all master to communicate each other, and the can receive the data from another TMS570. So TMS570 can send the data, but cannot receive the data. I doubt that the problem should be SCS, the SCS don't select the slave. Is it right?And how to solve it?

 I upload the code with MINSPI5, can you find the problrem? I puzzled fpr several days, the problem will make me crazy.

0131.MIBSPI.zip

I use the HALCoGen 4.00.00 and IAR 6.3.0 compiler

thanks in advance.

Hi, thanks for the code and the screenshots - I'll look into them.

user4205241 said:

in my opinion, the SCS0 should be low always, why this signal have pulse. 

This seems normal / correct to me;  the CSDEF set's the default value of the Chip select when there is no activity.  So 0xFF means the chip selects are '1's when inactive.  There is some inactive time between transmissions so it makes sense to see the pulse high.

If you don't want the chip select at all you can simply make the SPI work without chip selects - 3 pin mode - set all the chip selects to GIO mode.

Hi,

I loaded your slave program, but i'm seeing that the MibSPI5 FUN register has the value 0x0F0F0E0F in it.
This will be a problem for 2 reasons I think. 1st is you've got more than chip select 0 enabled. 2nd is that the quad data mode is enabled, which means that your transfer will complete after only a few (4) clocks rather than the 16 clocks you are expecting.
So I think this needs to be fixed. It may work after that because it looks ok otherwise.

But if you fix this and still have trouble - pls. let me know what values you see in the MibSPI registers and in the MibSPI RAM before and after you try to send data to it from the master. For the MibSPI RAM I am mostly interested in address 0xFF0A0200 because this has the status.

Thanks and Best Regards,
Anthony

Hi
I have solve the problem. In HALCoGen, I have set the CS[1] through SCS[5] as GIO pins, then I generate the code. But the code still set the CS[1] through SCS[5] as SPI pins.
I will debug the code continuely. Maybe I will seek help for you later.
Can you give me your E-mail to contact. My E-mail is zhuzl_sciyon@163.com, thank you

Hi User4205241 - I filed a ticket on this issue because HalCoGen doesn't give the option to configure CS[1] ...[5] yet it sets them as chip selects which is causing a problem. Ticket is SDOCM00114335.
My email is in the system here - you can click on my name and send me a message. But honestly it's better to post to the forum because we measure response times on the forum and there is always someone assigned to monitor it. This just happens to be my week.