SDRAM on EPI: no ALE?

Mike Frank

Other Parts Discussed in Thread: TM4C129XNCZAD

I am going to hang an ISSI SDRAM (IS42S16800F) on the EPI. Address and data are muxed, but I don't see an address latch enable output. How does this work?

Does the controller only use a limited set of the SDRAM modes? I've seen the Micron part recommended a few times here, which suggests that it works, but I don't see how when I look at the SDRAM timing diagrams. I'm not inclined to use the Micron part because it doen't look like micron intends to make it much longer.

Thanks,

Mike

over 10 years ago

0 Mike Frank over 10 years ago

Prodigy 50 points

Forgot to add that I'm using the TM4C129XNCZAD.

0 Amit Ashara over 10 years ago in reply to Mike Frank

TI__Guru**** 244400 points

Hello Mike,

In SDRAM mode the RAS and CAS is used by the Memory to sample the Row and Column Address before the data phase. So effectively you do not need an ALE.

Also we are doing a reference design for memory modules for TM4C129 which uses ISSI and Macronix memory parts (the sticky note on the forum has gone). The schematics and software would be coming up soon (expected 2 weeks)

Regards
Amit

0 Mike Frank over 10 years ago in reply to Amit Ashara

Prodigy 50 points

Ah, I thought it was something like that, but I couldn't find it in the SDRAM datasheet.

Thanks for your help,
Mike

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SDRAM on EPI: no ALE?