RAM Striping

Hi Amit 

Thanks for reply.

If Same Bank can also be be accessed by DMA.

Also what is the principle behind this??

Amit Ashara said:

Hello Sanjay,

Yes, same bank can be accessed by both uDMA and CPU. However the CPU will get priority when accessing the bank if both uDMA and CPU make an access at the same time. Thus uDMA will see a delay/latency in access. By having them simultaneously access different banks at the same time, the predictability in access time for uDMA is maintained, throughout the transfer.

Hi Amit,

How are the banks arranged? Is it just split down the middle, so DMA to the bottom half of SRAM can occur while the CPU accesses the top half?

Thanks, Rob

Thanks, Amit. I'd been thrown off by the use of the term "striping" without any mention of how it relates to the SRAM bank structure. The information I was looking for was contained in the note at the end of section 8.2.1, which doesn't mention striping.

EDIT: Further to this, the equivalent section in the TM4C123GH6PM datasheet is slightly clearer than that for TM4C1294NCPDT:

"The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay."

Am I right to assume that the TM4C1294NCPDT SRAM is similarly arranged, so one bank contains words [0, 4, 8...], another holds [1, 5, 9..], a third bank contains [2,6,10...] and the last has [3, 7, 11...]?

Actually, this post (and subsequent confirmation) suggests that the banks are not interleaved word-by-word on TM4C194x.