N2HET for high resolution PWM

Magnus,

Yes this is possible. 12 bit resolution means 1 part in 4096. 4096 x 20KHz = 81MHz, so you will just be over 12-bits with a 90MHz VCLK2. You of course need to use the HR mode of the PWM instructions and have HRP = 1 so that your hi-res clock is also 90MHz.

As I understand, its not that simple.
The archived resolution also depends on the Loop Resolution Period as the pin action only takes places at the end of one. On the other hand thats intrinsically connected to the number of cycles/instrunctions needed. So take for example, you will need at least 2 instructions for the PWM (CNT and ECMP/MCMP), which leads you to select a LR Pre of 2(2^1) such that HR*LR=2 cycles.This will give you 22.22ns of LR Period.
So, in 20khZ you've got (1/20e3)/(22e-9)=~2250 divisions (possible positions to the pin action to take place), equivalent to log2(2250)=11.13 bits of resolution.
Thats the best case scenario where you dont use the N2HET to anything else and got only these 2 instructions.

Did I got it right, or am I missing something?

Regards

Hi TBGomes,
Yes - you're missing he concept of the HR structure. There is a 7 bit hardware counter (high resoultion structure) associated with each N2HET pin.
Instead of scheduling the edge for the start of the next loop resolution period - if you set the hr_lr = high option in the ECMP/MCMP instruction, the pin action is scheduled for next LRP + some delay and the delay value has the resolution of the HR clock.
So there is a limit tied to the LRP but it's for the period, not the duty cycle. You can only schedule one edge per pin during each LRP so your period has to be > 2 LRP. But the duty cycle can be set anywhere within the period down to the resolution of the HR clock.
Also, with a single ECMP/MCMP your period is usually limited to some integer number of LRP's.
If you need better resolution on the period as well, you can achieve this with the use of the XORSHARE feature and by combining
two channels onto 1 pin ... but that's kind of advanced.
Last - you need at least +1 cycle for your code to branch back to address 0x00.. So if you were using a 2 cycle program you'd actually need at least a 3 cycle LRP - (which means it's likely you have to set LRP to /4 since there's no /3 option...)
-Anthony

Indeed,

I missed that.
I was using the halcogen default pwm codes, which does not include the use of this feature (at least I could not find it).
So tricked it and changed the setduty function and archived the HR clock resolution.

Thank you

Yes, the program that generates the PWMs in HalCoGen uses the PWCNT instruction in loop resolution mode.
So the period and duty cycle of this program become multiples of the loop resolution period.

The basic PWM 'kernel' that is used in the HalCoGen program is posted here: e2e.ti.com/.../test_5F00_pwcnt_5F00_2.zip
(just the PWM part). You can play with it in HET IDE and perhaps change the resolution to high to see what happens.

There's a pretty long discussion on this post - on the topic of PWMs: e2e.ti.com/.../1403944

One of the links in that post is to a different PWM program that will generate 0 to 100% duty cycle symmetric PWMs with deadband and also with hi-res period and duty cycle adjustment.