Number of cycles for Interrupt Latency

Sindhu Krishna

What is the Interrupt Latency cycles in TMS570 MCUs (Cortex R4, R4F and R5F) ? Is there any supporting documents available to explain about this ?

What are the pipelining stages in Cortex R4, R4F and R5F ? The number of cycles involved for the same ?

over 10 years ago

0 Chuck Davenport over 10 years ago

TI__Guru 59540 points

Hello Sindhu,

I have forwarded your question to one of our architecture experts. However, I believe you will find what you are looking for in the cpu specific TRMs available on the ARM website.

0 Charles Tsai over 10 years ago in reply to Chuck Davenport

TI__Guru**** 191886 points

Hello Sindhu,
You can find similar post and answer at http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/247260. You can try to measure the latency either by using the CPU's built in PMU or toggle the GIO at the beginning of the ISR and measure the time difference.

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Number of cycles for Interrupt Latency