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TIVA GPIO SDRAM

TIVA documentation in the section on configuring GPIO for EPI use with the SDRAM option mentions configuring the GPIO ports for alternate function select (EPI), 8mA drive strength, and slew rate control.  I am testing a 129 connected to an AS4C4M16S SDRAM;  the SDRAM controller completes its initialization but I am unable to read/write to the part (always reading 0s).  Bus us at 60 MHz.  GPIO lines appear to be set up correctly, a dump of the GPIO control registers shows them to be in the proper mode (8mA, alt fctn selected, port control F).

Is there a reference for further guidance on GPIO setup?  For example, do all EPI pins tied to the SDRAM need to have 8mA and slew rate control enabled?  (In the absence of other info, that is what I have done).  Is there a more specific order of setup?  And, do the pull up or pull down features on the port need to be enabled?  (Do they even apply once alternate functions are enabled?)


Thanks much!

  • Hello Tim,

    Can you share the Software code you are using?

    TivaWare has an example for C:\ti\TivaWare_C_Series-2.1.0.12573\examples\peripherals\epi\sdram.c which shows the configuration and I have used for testing with ISSI and Micron SDRAM memories w/o any issues. If the same configuration is present then we may need to see the board schematics and layout for any probable HW issue.

    Regards
    Amit
  • Thank you, Amit, for pointing me to this. The older version I had did not have an SDRAM example. This one worked fine. I was setting up the GPIO lines using more cumbersome function calls; after simplifying using the method presented in the example, the tests worked. BTW, within the SDRAM code, there is a table lookup based on sys clock rate. The table erroneously has two entries where the frequency is 50,000,000, though the comment above the 2nd entry suggests it should have been 30MHz.

    Regards,

    Tim
  • Hello Tim,

    Yes it is based on the table entry and glad it worked (board issues are more tougher to diagnose/fix remotely).

    Thanks for pointing to the incorrect entry.

    Regards
    Amit
  • Hello Amit,


    Though I had some success over the weekend, I noticed today that SDRAM is now broken, in a very specific manner.  I had tested SDRAM overnight with random and counting data patterns, and it worked fine. 


    I noticed today that the SDRAM now always reads as 0000 0001 0002 0003....  wrapping back to 0 after 03ff, starting at address 0x8000_0000 where it is mapped in.


    I re-burned the last load that worked on Sunday, cycled power, and noted the same erroneous results, eliminating the question of whether or not I had introduced any changes in the software.

    The pattern suggests that I am reading back the column address rather than the data.  This may suggest that the SDRAM was not configured successfully, and I am wondering about the GPIO timing and skew.

    The example had no specific calls to apply slew control to the GPIO signals associated with SDRAM; yet the manual (paragraph 19.4, step 4 of configuration) suggests that slew control should be applied to some or all signals.  Also, there is not good description of the effect that slew control has (other than a register that turns it on or off for each bit). 

    Can you provide some insight on slew control, and how it should be set for SDRAM control?  This is a Tiva-129 running at 120MHz;  the registers are set as indicated in the SDRAM.c example.

    Regards,

    Tim

  • Hello Tim,

    I checked the memory part mentioned here and a recent post with similar issue. The parameter in SDRAM configuration needs to be redone

    http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/392432

    Regards
    Amit
  • Thanks, Amit, for the quick response.

    My last error was an operator error; I found that later in the execution some GPIO lines were reconfigured by some test code which presumed the 129 eval board, thereby interfering with GPIO use for SDRAM access. Having removed that code, things are back to normal.

    Thanks once again,

    Tim
  • Hello Tim,

    Nice. But do take care of the SDRAM Size as well during configuration.

    Regards
    Amit
  • Thanks. I had determined our part was smaller than the one used in the example over the weekend, so I am all set to go.

    Tim