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Hi-z setting of GPIO

Sh.Sasaki
Guru 13625 points
Other Parts Discussed in Thread: TMS570LS1227, HALCOGEN

Hi

I have a question about Hi-z setting of GPIO.

Device : TMS570LS1227

(1) GIODIR & GIOPDR & GIODOUT is set. 

(2) GIODIR is not set

Both (1) and (2) terminal setting is the Hi-z.

Is there a difference in behavior in (1) and (2) ?

Do you have the recommended method when I set the terminal to Hi-z ?

Regareds,

FSSer

  • 0
    TI__Genius 11645 points
    Hi FSSer,

    Will have one of our experts comment on it, but I believe Method(1) is preferred.
  • 0
    TI__Mastermind 20030 points

    Dear FSSer,

    Option #1 defines an open drain configuration in which you are driving low when GIODOUT is 0 and allowing an external pull-up to set the voltage when GIODOUT is 1. This configuration is excellent for communicating (slowly) with devices that have different I/O voltage rails or a wired-AND configuration in which any of multiple nodes can pull a signal low. This option is OK, but it will be low impedance only while GIODOUT is 1.

    Option #2 will prevent the outptu from driving independent of the value in GIODOUT.

    So, you are correct that both configurations will not drive the pin.

    In option #1, you expect an external pull-up resistor to be present (because this is the typical open drain configuration). In option #2, you can

    • configure an internal pull-up or pull-down

    or

    • disable the internal pull-up/pull-down and supply an external resistor.

    If you do not bias the input, it is likely that the input will bias to mid-rail. A mid-rail bias tends to leave some current path in the input buffer since both nmos and pmos transistors are partially-on. Therefore, whichever option you choose, it is recommended to bias the pin so that the input does not float.

    Best Regards,

    Kevin Lavery

     

  • 0 in reply to Kevin Lavery
    Guru 13625 points

    Hi Kevin,

    Thank you for your reply.

    In option #1, you expect an external pull-up resistor to be present (because this is the typical open drain configuration). 

    Don't use the internal pull-up resistor at open drain configuration?

    I looks like an internal pull-up is available in HalCoGen.

    Best Regards,

    FSSer

  • 0 in reply to Sh.Sasaki
    TI__Mastermind 20030 points

    FSSer,

    The Technical Reference Manual shows a table on the last page of the GIO chapter (SPNU515A, Section 25.6) which shows that the internal pull is disabled in open-drain mode. (I had difficulty pasting the graphic so that is why I am citing it rather than just showing it in the post.)

     

    Best Regards,

    Kevin Lavery

  • 0 in reply to Kevin Lavery
    Guru 13625 points

    Kevin,

    I'm sorry. I didn't check the TRM.

    Now, I found that table.   --> "Table 25-22. Output Buffer, and Pull Control Behavior for GIO Pins"

    Thanks & Regards,

    FSSer