RM48L952ZWT MibSPI3 Chip Select

Update: I changed the buffer length to 128, instead of 127 and it is working fine now. Why would this cause it to fail for cs1 where it passed for cs0? I noticed the test case utilizes 127 bytes sized transmission and not 128. D_SIZE is intialized to 127, and is used in the loadDataPattern routine.

Can you please clarify?

Secondly, how can I test to verify ENA is working properly in the loopback example?

Ubaid

Hi Ubaid,

Your query has been forwarded to an expert.

Thanks and Regards,

Vineeth

Hello Ubaid,

The buffer size of MIBSPI in this device is limited to 128. It is not possible to configure both the transfer group with size 127 beacuse the sum of lengths of the transfer groups should be less than 128. I hope HALCoGen throws a warning if it exceeds.
Please reconfigure your HALCoGen settings accordingly.

Can you please clarify on what buffer lengths you used later? (which transfer group did you configure as length 128?)

For testing the ENA pin functionality, Analog loopback can be used with ENA pin set as functional. In Analog loopback mode in a master SPI, ENA signal is also generated by internal logic and hence its functionlaity is automatically tested. In this mode, it is also possible to induce errors like desync/timeout error (which are related to ENA pin).
Is this what you were looking for? Please refer section in 24.3.2 in RM48x Technical Reference Manual for more details.

Hope this helps!

Thanks and regards,
Veena

Hello,

I configured both buffer lengths to 128 for CS0, and CS1.  To understand this correctly, both CS0 and CS1 utilize part of the total 128 buffer?  If I utilize CS0,CS1,CS2,and CS3, the same applies and instead of 128 for each, one configuration option is 32 for each?

Didn't see an explicit warning in the log, but I did see an "Undefine"  when i generatd the code for which there is no additional information for.

How can I verify the ENA pin is working as expected? What do I look for? Also, how can the errors be induced?  I reviewd section 24.3.2 as well as 24.9.42 in the manual, and I did not see how to explicitly veriy ENA, nor generated errors.

Thanks.

Ubaid

Hi Ubaid,

I got the following error while configuring the MISPI transfer group size (configured as 127+127).

I am using HALCoGen version 04.02.00

The 128 buffers in the MIBSPI RAM is shared among the 8 transfer groups (without overlap). For example, if you configure the TG0 size as 10 and TG1 size as 20, HALCoGen configures the first 10 buffers for TG0 and the following 20 buffers for TG1.The start buffers for these transfer groups are configured as 0 and 10 respectively. (in register TGCTRLx). HALCoGen assumes the sum of transfer groups size doesn’t exceed 128.

I assume the following happened when you configured both the transfer sizes as 128.

• It first configures the 128 buffers for TG0.
• Then it tries configuring the next 128 bytes. Since the RAM is full, it fails to configure that.
• The start buffer of TG0 is configured as 0.
• It tries to configure TG1 start buffer as 128. Since the register doesn’t support 8 bits for start buffer filed, it is configured as 0.

So, when you try to send TG1, it actually starts sending buffers 0-127 which is actually configured for TG0.

So, please configure transfer groups such that the sum of lengths does not exceed 128.

There are two ways to verify the ENA pin functionality.

One way is to transmit data in analog loopback test mode. If the ENA pin is configured as functional, a transfer will generate the ENA signal as well as poll for the signal (if ‘wait for enable’ is enabled). Same is the case for CS pins.

Use HALCoGen API mibspiEnableLoopback with parameter Analog_Lbk. Find below a sample code.

mibspiEnableLoopback(mibspiREG3, Analog_Lbk);

mibspiTransfer(mibspiREG3,0);

while(!(mibspiIsTransferComplete(mibspiREG3,0))) ;

Second way is to induce errors while transmitting data in analog loopback test mode. Find below a sample code to induce data length error.

mibspiEnableLoopback(mibspiREG3, Analog_Lbk);

mibspiREG3->IOLPKTSTCR |= 1 << 16; //Set CTRL DLENERR field to induce error

mibspiTransfer(mibspiREG3,0);

You can see the data length error flag set in SPIFLG register.

Same procedure may be used to induce other errors like timeout or desync error. (Refer IOLPKTSTCR for the corresponding bit)

Notes: Make sure ENA pin is functional and data format is configured such that ‘Wait for enable’ is enabled.

Sample code to induce CS error:

           uint32 cs = 0;

          mibspiEnableLoopback(mibspiREG3, Analog_Lbk);

mibspiREG3->IOLPKTSTCR |= (1 << 2) | (cs << 3);

          mibspiTransfer(mibspiREG3, 1);

This causes SCS FAIL FLG to set in IOLPKTSTCR to set.

Hope this helps!

Thanks and regards,

Veena

Hello Veena,

Thanks for the response.

I updated the transfer groups as you suggested.  Transfer group 0 has 64 bytes and Transfer group 1 has 64 bytes as well.  Chip select 0 (transfer group 0) passes the loopback test, but chip select 1 (transfer group 1) fails.  I modified the source code so that:

#define D_SIZE      63

instead of 127 from prior.  Is any additional configuration is needed for chip select 1 to work?  Below is the screenshot of the updated transfer group configuration. 

Also, what is the implication on the bit rate now that the length has been reduced from 128 to 64?  How can the bit rate be calculated?

RE: "Notes: Make sure ENA pin is functional and data format is configured such that ‘Wait for enable’ is enabled."

ENA is functional and "Wait for enable" is enabled under the data format tab.  The loopback test does not complete and PASS/FAIL criteria is not triggered.  Now that "Wait for enable" is enabled, how must the test code be modified ?

Thanks.

Hi Ubaid,

I tried an error forcing test using both the transfer groups. And I could see the error flag set in both the cases. I don't see any reason why it should fail in case of TG1. Can you please share the project so that i can try from my side.

There are 2 things to take care for a CS pin to be active - 1) set the pin as functional 2) Pinmux config (It is enabled by default). Do check both the places.

The bit rate remains the same (as configured in the corresponding Data format) irrespective of the length of the transfer group. The only difference is that it will send 64 16-bit data in one-go instead of 128.

Regards,

Veena

Hello Veena,

I am attaching my HalcoGen project and test code for loopback.

NOTE: MibSPI3 Data Format has "Wait for enable" is not checked for Data Format 0.  If checked, the loopback test does not return PASS/FAIL.  This will need to be enabled to properly test ENA from my understanding.

NOTE 2: mibspiInit(); is called at a higher level.

With the current configuration chip select 0 (mibspiCS0DriverTest()) passes, and chip select 1 (mibspiCS1DriverTest()) fails.  

8512.Halcogen_mibSPI.zip

Ubaid

Attaching mbispi.c and.h, but this should be auto-generated from HalcoGen project file I provided earlier.

6076.mibspi.c

4784.mibspi.h

Hello Veena,

Wanted to see if you had any progress in understanding why my code would not work.  Please advise as I need to root out any issues with SPI in the next day or two.  This includes properly testing ENA.

Also, I wanted to ask if mibSPI3 can be used to communicate with two slave devices, where only one of them has the ENA line connected?  The ENA line will be connected to only 1 slave device.  Would I use two different Data Formats where one of them has "Wait for Enable" checked and the other doesn't to accomplish this?

Thanks

Ubaid

Hi Ubaid,

Answering your second question on MIBSPI being used to communicate with 2 different slaves..

You are correct. You have to use 2 different data formats with one having 'Wait for enable' enabled and the other having it disabled.

Make sure you configure the data formats correctly in the Transfer Groups Tab. All the transfer groups are configured with data format 0 by default. (Also from the snapshot you sent I see both Transfer groups configured for data format 0).

Let us know if you have any trouble in doing this.

Thanks and Regards,
Veena

Hello Ubaid,

By enabling 'Wait on Enable' the master waits for the ENA pin to be active before enabling the clock. I am not sure whether that happens in case of an internal loopback. It tests only the transmit and receive path.

I advise you to use Input/Output Loopback mode where the externals pins are also being tested. To enable Input/Output Loopback mode use HALCoGen function mibspiEnableLoopback (using register IOLPBKTSTCR) instead of mibspiEnableInternalLoopback.

Refer section 24.3 in RM48x Technical Reference Manual for more details on these two loopback modes.

Thanks and Regards,

Veena

Hi Ubaid,

Can you please share the code?

Thanks and Regards,

Veena

Hello Veena,

Below is the source code.  This would be the "normal case", and will uncomment lines below to induce specific errors.  Halcogen has been configured such that chip select 0 has "Wait for enable" enabled.   The only change not included below is printing of mibSPi3->IOLPKTSTCR and mibSPI3->FLG (for SPIFLG).

void mibspiCS0DriverTest(void)
{

	uint8   mibspiTest = PASS;
	int i;

   /* - creating a data chunk in system ram to start with ... */
   loadDataPattern(D_SIZE,&TX_DATA[0]);

   /* - enabling loopback ( this is to emulate data transfer without external wires */
   mibspiEnableLoopback(mibspiREG3, Analog_Lbk);

//Below line to enable data length error
//   mibspiREG3->IOLPKTSTCR |= 1 << 16; //Set CTRL DLENERR field to induce error

//Below line to enable CS error
//   mibspiREG3->IOLPKTSTCR |= (1 << 2) | (/*cs*/ 0 << 3);

   /* - assigning dma request: channel-0 with request line - 1 */
   dmaReqAssign(0,15 );

   /* - configuring dma control packets   */
   dmaConfigCtrlPacket((uint32)(&TX_DATA),(uint32)(&(mibspiRAM3->tx[0].data)),D_SIZE);
   /* upto 32 control packets are supported. */

   /* - setting dma control packets */
   dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);

   /* - setting the dma channel to trigger on h/w request */
   dmaSetChEnable(DMA_CH0, DMA_HW);

   /* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1     */
   /* - refer to the device data sheet dma request source for mibspi tx/rx  */
   mibspiDmaConfig(mibspiREG3,0,0,15);
   
   /* - enabling dma module */
   dmaEnable();

   /* - start the mibspi transfer tg 0 */
   mibspiTransfer(mibspiREG3,0 );

   /* ... wait until transfer complete  */
   while(!(mibspiIsTransferComplete(mibspiREG3,0)))
   {
   };

   /* copy from mibspi ram to sys ram */
   mibspiGetData(mibspiREG3, 0, RX_DATA);

   for (i = 0;i < D_SIZE; i++)
   {
     if (TX_DATA[i] != RX_DATA[i])
     {
    	mibspiTest = FAIL;
     }
   }
   if (mibspiTest == PASS)
   {
     sciSend		(scilinREG, 52 , (unsigned char *) "\r\nMIBSPI CS0 Test Loopback .................. PASS\r\n");
   }
   else
   {
     sciSend		(scilinREG, 52 , (unsigned char *) "\r\nMIBSPI CS0 Test Loopback .................. FAIL\r\n");
   }

}

Hi Ubaid,

Just to keep test simple, is it OK if I give you sample code with out DMA and testing this functionality? 

Hello,

Yes sure.  My purpose is to confirm MibSPI3 with chip select 0 (ENA enabled) is working properly and to also be able to confirm ENA is working properly.

Thanks.

Ubaid

Hi Ubaid,

If your initial question was answered, please close this thread by marking ALL correct answers.

Thanks and Regards,

Vineeth