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RM48L952ZWT MibSPI3 bit rate?

Ubaid Mahmood
Intellectual 970 points
Other Parts Discussed in Thread: RM48L952

In reference manual spnu503b on page1042, it indicates that mibSPI supports up to 20 MHz baud rate.  I did not see information as to what bit rate is supported.  Can you please help clarify the bit rate?

Thanks

  • 0
    TI__Mastermind 49120 points

    Hello,

    The actual bit rate supported by each SPI interface is specified in the particular part's datasheet. For the RM48L952 MCU, SPNS177 specifies:

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Intellectual 970 points

    Hello Sunil,
    Thanks for the information. I am unable to interpret this table, can you please help me interpret it? Not clear what the first column is for, and not clear if the value 40 for the "MIN" column refers.

    For MibSPI3 with 2 chip selects enabled, what would the bit rate be? I noticed some timing estimates for ENA, which we do plan on enabling.

    Thanks.
    Ubaid

  • 0 in reply to Ubaid Mahmood
    TI__Mastermind 49120 points
    Hello Ubaid,

    The timings specified in the datasheet apply to each instance of MibSPI and SPI. Section 5.9.4 describes the I/O timings for all MibSPI/SPI interfaces on the RM48L952 MCU.

    Figures 5-9 and 5-10 show timings pertinent to the SPI protocol. Each significant timing parameter is marked by a number. This number is referenced in table 5-22 in the first column.

    For example, parameter # 1 specifies the clock period of the SPICLK signal, or the bit rate of the interface. This is specified to be a minimum of 40ns, so that the SPICLK frequency (or SPI bit rate) can be as fast as 25MHz, but not faster. Each MibSPI/SPI takes in VCLK and divides it down by a programmable value to generate the SPICLK. This divider must be programmed correctly to not exceed the max bit rate specified in the datasheet.

    Also, the bit rate is not dependent on the number of chip selects enabled. I am not sure I understand your question related to chip selects and ENA. Can you please clarify?

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Intellectual 970 points

    Thanks Sunil,

    I appreciate your explanation.

    You mentioned 25MHz, which is 25 cycles per second. How can this be converted to bits per second? how many bits per cycle?

    How is the calculation for Parameter 10 , SPIENA used?  What does this value indicate exactly?


    Thanks.
    Ubaid

  • 0 in reply to Ubaid Mahmood
    TI__Mastermind 49120 points

    Ubaid,

    25MHz = 25 million cycles per second. On each SPICLK cycle MibSPI/SPI can send and receive a single bit on each available SIMO/SOMI line.

    Check table 5-18 in spns177b.

    As you can see MiBSPI1 and MibSPI5 support multiple SIMO and SOMI lines. This allows you to output / input more than one bit each cycle, thereby improving the bandwidth of the interface.

    There is also a "dead time" of 6 VCLK cycles between successive transfers. You can use this information along with the information about the amount of data to be transferred and the character length (number of bits per transfer) to calculate the actual bits per second for the selected MibSPI/SPI interface.

    Regards, Sunil