sd card on EK-TM4C123GXL laucnhpad

Hello Glenn,

You can use on the SD-CARD Booster Packs for EK-TM4C123 and then port over the example from DK-TM4C123 for sd_card

http://www.ti.com/ww/en/launchpad/boosterpacks.html?keyMatch=boosterpacks&tisearch=Search-EN

Regards
Amit

Hi Amit,

Along these same SD-CARD lines - is TM4C SW & HW compatible with newer, larger capacity, SD-HC format cards? (we know this caused difficulty under older Stellaris - unsure of this ability - now.)

SD-HC dominates in all of the higher capacity SD Cards - we find only "bottom of the barrel" in plain SD format...

Looked at the boster packs. Could not find associated software with them.

I have ported FATFS on TI M3 devices. The question I have is that I am used to having to manually set the chip select for spi devices.
In the example for spi_master.c the following sequence of code is used.

GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);

//
// Configure the GPIO settings for the SSI pins. This function also gives
// control of these pins to the SSI hardware. Consult the data sheet to
// see which functions are allocated per pin.
// The pins are assigned as follows:
// PA5 - SSI0Tx
// PA4 - SSI0Rx
// PA3 - SSI0Fss
// PA2 - SSI0CLK
// TODO: change this to select the port/pin you are using.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
GPIO_PIN_2);

Here the chip select pin PA3 appears to be managed by the spi drivers.

One Question
What if one has multiple devices tied to a spi port. This model would not work. How would one set up the spi port to use chip selects that were managed by the user?.

On the grove shield, the pins are
clk pin 7 -- pb4 ssi2clk
miso pin 14 -- pb6 ssi2RX
mosi pin 15 -- pb7 ssi2TX
cs pin 12 -- pa3 --- not part of SSI2 configuration. In this case, the spi chip select appears to be manually managed.

Hello Glenn,

The sd-card requires the CS to be low for the transfer while the SPI on TM4C123 toggles it after every transaction. Even in the continuous mode, if the CPU goes to handle an interrupt and SSI FIFO empties, the FSS would have toggled back to 1.

Thus the CS or FSS is GPIO controlled under software.

Regards
Amit

Hello cb1

Thanks for the pointer. It is something that we need to check.

Regards
Amit