tms570-regarding clocks

Hi Pavithra,

Let me try to answer questions in your first post.

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for tms570lc4357 it is mentioned that crystal frequency range is 5-20 MHz and maximum frequency that can be achieved through PLL is 300MHz.

>> That is not what the datasheet specification means. The input main oscillator frequency range is limited from 5MHz to 20MHz. You can choose any oscillator with frequency in this range. However, the max frequency that you can achieve through PLL is not limited to 300MHz. The 300MHz maximum applies to the CPU clock domain frequency. That is, the CPU can only operate up to a frequency of 300MHz.

>> The PLL timings are specified in section 5.6.1.3.2 "PLL Timing Specifications" in the LC4357 datasheet (spns195). As you can see, the PLL can output a maximum frequency of 400MHz.

1. what is the minimum crystal frequency required to achieve 300MHz?

>> You can get a 300MHz clock output from the PLL even using the minimum 5MHz frequency oscillator. You can use HALCoGen to configure the PLL. First go to the "Clk Source" tab and input 5.0 as the "Crystal Frequency". Then go to the PLL tab and play with the input divider, the multiplier (feedback divider), and the two sequential output dividers to get the output frequency you desire. You need to consider the min and max frequency ranges specified for each intermediate stage while choosing a value.

2. if 5MHz crystal is used what is the maximum frequency that can be achieved?

>> As shown in the above figure, you can get to the max CPU operating frequency using a 5MHz crystal as well.

3. in HDK 16MHz crystal is used. Is that the recommended crystal osc freq? if not what all can be used??

>> The choice of the oscillator and its frequency is entirely up to you. The only constraint is that it needs to be within the range of 5MHz to 20MHz.

4. if 300MHz can be achieved using 16MHz and 20MHz, what is the difference between both? for example in terms of current or power consumption.

>> The difference in power consumption for a 16MHz versus a 20MHz oscillator is negligible, unless you are using these parts for a low-power mode application in which the main oscillator is kept active even through the low-power phase of operation.

5. usually we will be using maximum frequency(300MHz). if we use max freq, whether recommended baud rates for

 --> flexray-1.25Mbps, 2.5Mbps, 5Mbps, 10Mbps

>> The FlexRay controller requires an 80MHz clock signal on the VCLKA2 clock domain. This signal is usually provided by generating an 80MHz output from PLL2.

 --> ethernet - 10Mbps,100Mbps

>> The Ethernet operating mode is defined by the external oscillator that you use for the external Ethernet PHY. This is specified in the IEEE 802.3 standard as:

For an MII protocol

• 2.5MHz at 10Mbps, and
• 25MHz at 100Mbps

For RMII protocol, you need a 50MHz crystal input to the Ethernet PHY for both 10Mbps and 100Mbps.

 -->CAN - 125Kbps, 250Kbps, 500Kbps, 1Mbps

>> The CAN baud rate is generated using the VCLKA1 clock domain. This signal must be at least 8MHz to support a max transfer rate of 1MBaud. So if you want to use the main oscillator as the source for VCLKA1 (typical case), then the oscillator must at least be 8MHz if you want a max transfer rate of 1MBaud. The other transfer rates can be achieved even with a 5MHz oscillator, or by using VCLK as the source for VCLKA1 domain.

 --> SCI - 9600bps, 115200bps can be achieved with 0% tolerance?

>> The baud rate for SCI is generated from VCLK and is not (directly) dependent on the oscillator frequency. Again, you can use HALCoGen to determine the VCLK frequency you need to meet the exact SCI baud rate required with 0% tolerance. See the "SCI Data Format" tab for each instance of the SCI module.