My code is listed below. All is ok except the ready signal , PK4 is not working. Please help me , thanks very much!
void Epi_init()
{
uint32_t ui32Val;
int i;
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. Please refer to the datasheet for more information about pin
// muxing.
//
//
// EPI0S00 ~ EPI0S03, H0 - 3
//
ui32Val = HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTH_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S24, EPI0S25, EPI0S31 : K0 ~ 3, K7, K6, K5
//
ui32Val = HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL);
ui32Val &= 0x00F0FFFF;
ui32Val |= 0xFF0F0000;
HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTK_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S4 ~ EPI0S7: C4 ~ 7
//
ui32Val = HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL);
ui32Val &= 0x0000FFFF;
ui32Val |= 0xFFFF0000;
HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTC_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S8 ~ EPI0S9: A6 ~ 7
//
ui32Val = HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL);
ui32Val &= 0x00FFFFFF;
ui32Val |= 0xFF000000;
HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTA_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S10 ~ EPI0S11: G0 ~ 1
//
ui32Val = HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFFFF00;
ui32Val |= 0x000000FF;
HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTG_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S12 ~ EPI0S15: M0 ~ 3
//
ui32Val = HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTM_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S16 ~ EPI0S19, EPI0S26: L0 ~ 3, L4
//
ui32Val = HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFF00000;
ui32Val |= 0x000FFFFF;
HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTL_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S20 ~ EPI0S23: Q0 ~ 3
//
ui32Val = HWREG(GPIO_PORTQ_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTQ_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTQ_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S27, EPI0S28 : B2, B3
//
ui32Val = HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF00FF;
ui32Val |= 0x0000FF00;
HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTB_BASE + GPIO_O_DR8R) = 0xFF;
//
// EPI0S29 ~ EPI0S30: P2 ~ 3
//
ui32Val = HWREG(GPIO_PORTP_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF00FF;
ui32Val |= 0x0000FF00;
HWREG(GPIO_PORTP_BASE + GPIO_O_PCTL) = ui32Val;
HWREG(GPIO_PORTP_BASE + GPIO_O_DR8R) = 0xFF;
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
//
GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);
GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);
GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);
GPIOPinTypeEPI(GPIO_PORTP_BASE, EPI_PORTP_PINS);
GPIOPinTypeEPI(GPIO_PORTQ_BASE, EPI_PORTQ_PINS);
EPIModeSet(EPI0_BASE, EPI_MODE_HB8);
//EPIClk = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) *2))
//EPIDividerSet(EPI0_BASE, 1);
EPIDividerSet(EPI0_BASE, 6);//6
EPIConfigHB8Set(EPI0_BASE, EPI_HB8_IN_READY_EN, 200); //maxwait<256
//EPI_HB8_IN_READY_EN_INVERT
//WAIT_0: 2EPI clocks,WAIT_1: 4EPI clocks,WAIT_2: 6EPI clocks, WAIT_3: 8EPI clocks,
// EPIConfigHB8CSSet(EPI0_BASE, 0, EPI_HB8_MODE_ADDEMUX | EPI_HB8_WRWAIT_0 | EPI_HB8_RDWAIT_0 );
EPIConfigHB8CSSet(EPI0_BASE, 0, EPI_HB8_MODE_ADDEMUX | EPI_HB8_WRWAIT_1 | EPI_HB8_RDWAIT_1 );
EPIConfigHB8CSSet(EPI0_BASE, 1, 0x01000000);
// EPIConfigHB8TimingSet(EPI0_BASE.0,0);
/*EPI_HB8_IN_READY_EN_INVERT EPI_HB8_WORD_ACCESS
EPIConfigHB16CSSet(EPI0_BASE, 0, (EPI_HB16_CSCFG_ALE_DUAL_CS | EPI_HB16_ALE_HIGH | EPI_HB16_WRWAIT_0 |
EPI_HB16_RDWAIT_0 | EPI_HB16_CSCFG_ALE | EPI_HB16_BSEL));
EPIConfigHB16CSSet(EPI0_BASE, 1, (0x03000000 | EPI_HB16_ALE_HIGH | EPI_HB16_WRWAIT_0 |
EPI_HB16_RDWAIT_0 | EPI_HB16_CSCFG_ALE | EPI_HB16_BSEL));
*/
//EPIConfigHB16TimingSet(EPI0_BASE, 0, (EPI_HB16_WRWAIT_MINUS_ENABLE|EPI_HB16_RDWAIT_MINUS_ENABLE));
//EPIConfigHB16TimingSet(EPI0_BASE, 1, (EPI_HB16_WRWAIT_MINUS_ENABLE|EPI_HB16_RDWAIT_MINUS_ENABLE));
/*EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_PER_SIZE_256MB | EPI_ADDR_PER_BASE_A
| EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6) );
EPIAddressMapSet(EPI0_BASE, (EPI_ADDR_PER_SIZE_16MB | EPI_ADDR_PER_BASE_A | EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6) );
*/
EPIAddressMapSet(EPI0_BASE, ( EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6) );
}
