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Using single core(Cortex-R) in RM57L843

Kummi
Mastermind 6220 points

Other Parts Discussed in Thread: RM57L843, RM48L952, TPS65381-Q1

Hi,

We would like to know if it is possible use single core Cortex-R in Hercules.

One of customer's application needs processor with Speed >220MHz(300DMIPS) and
inbuilt Flash(2 to 4MB). Sitara(AM335x) would be High spec and TIVA C is low spec,
so we believe the only available solution is Hercules.

1. As this is not a Safety related application, can we use only one core in this MCU?

2. And the application needs external 16MB of SRAM with ECC...
    Does RM57L843's EMIF interface support external SRAM with ECC?

Best Regards
Kummi

  • 0
    TI__Mastermind 22715 points
    Kummi,

    1. On this device two CPUs runs in lockstep. there are no other options.
    2. No ECC for external memory. Please read the EMIF errata for this device to see if it suites your application.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Mastermind 6220 points

    Hi Zhang,

    Thank you so much for the quick reply
    and I am sorry for the delay..

    Regarding the EMIF errata (DEVICE#39), it mentions that if we use
    external RAM it is less efficient because of the redundant read or write cycles.
    Can we assume with this means the RAM access through EMIF will be slow because of
    the workaround(64-bit align access).

    Meanwhile,because of this errata we are also thinking about RM48L952 with
    external FLASH(1MB) and RAM(16MB).

    And regarding the Power Managment IC(PMIC), don't we have any other solution
    other than TPS65381-Q1? as this application is not safety critical, TPS65381-Q1
    could be high spec.

    Best Regards
    Kummi.

  • 0 in reply to Kummi
    TI__Mastermind 22715 points
    Kummi,
    To use external Flash and RAM with RM57L843, the only hardware waork aound is to "OR" the WE signal with DQM signals. To improve the CPU performance, you can make external memory cacheable. In the way, the cache controller will bring in a cache line (32 bytes) for each cache miss. The 64 bit reads does not have any impact on performance. On RM57L843, the user is responsible to maintain the cache/external memory coherence if there are multiple masters accessing external memory.
    We do not recoment executing from RM48L952 external memory because it is going to be really slow (at least 5 times slower compared to on-chip Flash). Please check the errata for other limitations.
    For RM57L843, the power supply for 1.2V has to supply at least 1A to ensure proper operation over temperature.
    Thanks and regards,Zhaohong