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SSI(slave)~DMA interrupts on TM4C1231H6PGE

Massimiliano Cialdi
Expert 1995 points
Other Parts Discussed in Thread: TM4C1231H6PGE

I use TM4C1231H6PGE.

I need to use SSI0 in slave mode with DMA for both TX and RX, and I need an interrupt to be issued when a DMA transfer is complete.

If I program the Interrupt as foolows:

static void SSI2RecvEndIntHandler(UArg unused)
{
    volatile unsigned long i;
    unsigned long v;
    v = ROM_uDMAIntStatus();
    ROM_uDMAIntClear(v);
    if((v&(1<<UDMA_CHANNEL_SSI2RX))!=0)
    {
	Semaphore_post(hSemRecv);
    }
}



    ROM_IntEnable(INT_SSI2);
    ROM_SSIIntDisable(SSI2_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR);
    Hwi_create(INT_SSI2, &SSI2RecvEndIntHandler, NULL, NULL);

two interrupts are issued as shows the D1 signal in this oscilloscope screenshot:

a TX interrupt is issued before the transfer is complete, and after, another interrupt is issued for RX.

But I cannot read the interrupt status from DMA because (from datasheet):

"When transfers are performed from a FIFO of the SSI using the μDMA, and any interrupt is generated
from the SSI, the SSI module's status bit in the DMA Channel Interrupt Status (DMACHIS) register
must be checked at the end of the interrupt service routine. If the status bit is set, clear the interrupt
by writing a 1 to it."

So what can I do?

best regards

  • 0
    TI__Guru**** 244440 points
    Hello Max

    What the line intends to state is that the interrupt from the peripheral is masked when used for DMA. The DMA only will trigger a done and the application code must check the DMACHIS to see if the DMA completion for the channel is set and then only read the Interrupt Status bit

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Expert 1995 points

    So, DMA trigger two interrupts, one for TX and one for RX, is that right?

    My application should verify if the interrupt is a TX or an RX interrupt, OK? I wonder how to verify the DMACHIS (TX or RX?) if it "must be checked at the end of the interrupt service routine"

    how should be the interrupt service routine?

    best regards

    max

  • 0 in reply to Massimiliano Cialdi
    TI__Guru**** 244440 points
    Hello Max,

    The TX and RX interrupts can be found by looking at the DMACHIS register as they are separate channels on the DMA. The CPU should, based on which bit is set read the Interrupt Status register of the peripheral and consider only that part of the read data which is applicable for the channel. As an example if the DMACHIS shows the channel for RX is complete then the SSIRIS/SSIMIS must be read and the bits corresponding to the RX be used to make a decision.

    Regards
    Amit