Can I get an explanation of Errata #39 Dummy WE/OE pulses in non-64bit asynchronous EMIF access? The errata is so poorly written, I am having trouble to understand how can I fix it. Is there a waveform diagram that shows which nDQMx gets active in what time when these dummy accesses appear? I would like to see one 16 bit asynchronous read and write access timing diagrams that show BAx, nDQMx, addresses, nCSx, nOE, and RnW, the way how they really happen including dummy pulses so that I can understand how to fix it.
Timing in the TRM figures 2-10 and 21-11 do not help since they do not specify how wide the access is and do not show nDQM signals separately. Based on the errata nDQM signals are key to fix this bug.
If someone has a logic diagram of the fix, that would help too.
Thank you.
Slobodan Gataric
