I am using the TM4C123G Launchpad Evaluation Kit. My problem is to read digital inputs from dip switches on port D pins (0-3) and replicate the digital output on port C pins (4-7). Regardless of the position of the dip switches, Kiel shows a single 1 in the first memory bit which I interpret as a locked port. Below is my code.
Help would be appreciated/
-----------------------------*;;
;;
;; Author: Hughes
;; Last Modified: 01/21/15
;;
;; Short:
;; Description:
;;
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PORTF_DATA_R EQU 0x400253FC
PORTF_DIR_R EQU 0x40025400
PORTF_AFSEL_R EQU 0x40025420
PORTF_PUR_R EQU 0x40025510
PORTF_DEN_R EQU 0x4002551C
PORTF_AMSEL_R EQU 0x40025528
PORTF_PCTL_R EQU 0x4002552C
PF2 EQU 0x40025010
PF4 EQU 0x40025040
SYSCTL_RCGCR EQU 0x400FE608
PORTC_DATA_R EQU 0x400063FC
PORTC_DIR_R EQU 0x40006400
PORTC_AFSEL_R EQU 0x40006420
PORTC_PUR_R EQU 0x40006510
PORTC_DEN_R EQU 0x4000651C
PORTC_AMSEL_R EQU 0x40006528
PORTC_PCTL_R EQU 0x4000652C
PC4 EQU 0x40006040
PC5 EQU 0x40006080
PC6 EQU 0x40006100
PC7 EQU 0x40006200
PORTD_DATA_R EQU 0x400073FC
PORTD_DIR_R EQU 0x40007400
PORTD_AFSEL_R EQU 0x40007420
PORTD_PUR_R EQU 0x40007510
PORTD_DEN_R EQU 0x4000751C
PORTD_AMSEL_R EQU 0x40007528
PORTD_PCTL_R EQU 0x4000752C
PD0 EQU 0x40007004
PD1 EQU 0x40007008
PD2 EQU 0x40007010
PD3 EQU 0x40007020
THUMB
AREA |.text|, CODE, READONLY, ALIGN=2
EXPORT Start_
Start_
bl Sys_Init_
Lab_Loop_
;;BL SSR_On
ldr r3,=PORTD_DIR_R
LDR r1,=PORTD_DATA_R
LDR r0,[r1]
and r0, r0, #0x0F
LDR r1,=PORTC_DATA_R
str r0, [r1]
bx lr
B Lab_Loop_
;;
;; Read CH4.2.1 and follow the steps outlined
;; in that section to initialize your I/O
;; pins.
;; 1- Activate clock for port
;; 2- Unlock the port (PC3-0, PD7, PF0)
;; 3- Disable analog input if present
;; 4- Disable alternate function
;; 5- Clear alternate function register
;; 6- Set DDR
;; 7- Enable port
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Sys_Init_
ldr r1, =SYSCTL_RCGCR ;; (1) Activate clock for given port
ldr r0, [r1]
orr r0, r0, #0x2C
str r0, [r1]
nop ;; allow time for clock to finish sync
nop
nop
;; 2) Unlock port if required
ldr r1, =PORTF_AMSEL_R ;; 3) Disable analog functionality (0: off; 1: on)
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTF_PCTL_R ;; 4) Disable alt. func. (PCTL_R -- Table 4.5)
ldr r0, [r1]
bic r0, #0x00000000
str r0, [r1]
ldr r1, =PORTF_AFSEL_R ;; 5) Set normal port function
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTF_DIR_R ;; 6) Set direction register (0: input; 1: output)
ldr r0, [r1]
orr r0,#0x04
str r0, [r1]
ldr r1, =PORTF_DEN_R ;; 7) Enable port
ldr r0, [r1]
orr r0,#0x04
str r0, [r1]
;;BX LR
;ldr r1, =SYSCTL_RCGCR ;; (1) Activate clock for given port
;ldr r0, [r1]
;orr r0, r0, #0x04
;str r0, [r1]
;nop ;; allow time for clock to finish sync
;nop
;nop
;; 2) Unlock port if required
ldr r1, =PORTC_AMSEL_R ;; 3) Disable analog functionality (0: off; 1: on)
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTC_PCTL_R ;; 4) Disable alt. func. (PCTL_R -- Table 4.5)
ldr r0, [r1]
bic r0, #0x00000000
str r0, [r1]
ldr r1, =PORTC_AFSEL_R ;; 5) Set normal port function
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTC_DIR_R ;; 6) Set direction register (0: input; 1: output)
ldr r0, [r1]
orr r0,#0xF0 ;; This makes port c pins 4-7 output
str r0, [r1]
ldr r1, =PORTC_DEN_R ;; 7) Enable port
ldr r0, [r1]
orr r0,#0xF0 ;; Enable port C pins 4-7
str r0, [r1]
;;BX LR
;ldr r1, =SYSCTL_RCGCR ;; (1) Activate clock for given port
;ldr r0, [r1]
;orr r0, r0, #0x08
;str r0, [r1]
;nop ;; allow time for clock to finish sync
;nop
;nop
;; 2) Unlock port if required
ldr r1, =PORTD_AMSEL_R ;; 3) Disable analog functionality (0: off; 1: on)
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTD_PCTL_R ;; 4) Disable alt. func. (PCTL_R -- Table 4.5)
ldr r0, [r1]
bic r0, #0x00000000
str r0, [r1]
ldr r1, =PORTD_AFSEL_R ;; 5) Set normal port function
ldr r0, [r1]
bic r0, #0x04
str r0, [r1]
ldr r1, =PORTD_DIR_R ;; 6) Set direction register (0: input; 1: output)
ldr r0, [r1]
bic r0,#0x00 ;; This makes port D pins 0-3 input
str r0, [r1]
ldr r1, =PORTD_DEN_R ;; 7) Enable port
ldr r0, [r1]
orr r0,#0x0F ;; Enable port D pins 3-0
str r0, [r1]
BX LR
ALIGN ; make sure the end of this section is aligned
END ; end of file
