Hello,
I am trying to configure as many GPIO pins as possible from MibSPI module (already explored other modules, like RTP, etc.). Based on RTM, it seems like the CLK and ENA are shared for all 5 sub modules. What I mean is the following
There are MIBSPI1CLK, MIBSPI2CLK...MIBSPI5CLK physical pins, so for ENA, yet there is only one bit, like CLKDIR in SPIPC1 register to control the CLK direction or CLKSET in SPIPC4 register. So SPI1,2,3,4,5 CLK must behave at the same time. Please confirm.
If so, what if I hook up MIBSPI1CLK to signal A externally and MIBSPI2CLK to signal B externally, for example, and I configure both CLK as general input pins but the signal A and B have different state (driven by external signals)? Is it prohibited situation? what is the value of CLKDIN bit in SPIPC2 register?
Thanks
Ning