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SPICLK Speed

pavithra pavithra
Intellectual 870 points
Other Parts Discussed in Thread: TMS570LS0432

hi ti,


in tms570ls0432 datasheet it s mentioned as 8-bti baud clock generator

in TRM it is mentione as 11- bit baud clock generator. which is correct????

it is also specified that the maximum baud rate is 20MHz.

in timing specifications , SPICLK minimum cycle time is 40ns. hence frequency is 25MHz....

why it s limited to 20MHz.....???

then in registers, if prescale is 0 then SPICLK = VCLK/2 = 40MHz...

which should be used????

  • 0
    TI__Guru**** 197386 points

    Hi Pavithra,

    Thanks for pointing out those confused values in TRM and Datasheet. My understanding is:

    1. 8-bit baud clock generator (SPIFMT[15:8])

    2. Supports max up to 20mHz baudrate

    I will forward this question to our TRM/Datasheet owner to confirm. Thanks

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 870 points
    thanks for your reply Wang.
    my question is why the speed the limited to 20MHz?? using that timing specifications we get 25MHz.
    can u pls explain me why it is limited...........
  • 0 in reply to pavithra pavithra
    TI__Guru 59540 points
    Hello Pavithra,

    - In regard to the baud rate generator, it is, in fact, an 11-bit baud rate generator. This was an enhancement that was made and is realized through the EXTENDED_PRESCALEx registers. The incorrect information in the description within the datasheet will be updated in the next datasheet update.

    - The 20MHz limit shown in the datasheet and the TRM are not correct and are carryover from a prior device. These limits will be removed from the module descriptions in the next update. You may use the timings within the timing tables as the guides for your SPICLK settings. i.e., 40ns is the minimum cycle time for SPICLK as you have mentioned.

    - In regard to the default, this is simply a description of that the module will do but note that a SPICLK = VCLK/2 will violate the timing requirements when VCLK > 50MHz. i.e., if VCLK/2 is greater than the allowed minimum cycle time, the prescalar must be programmed by the application.