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I used TMS570ls31x, I cannot download program to flash.

user4267432
Prodigy 200 points
Other Parts Discussed in Thread: TMS570LS3137, SEGGER, 4213

I was debugging the STC of the TMS570LS3137.And I met a problem that I could not download the program into the flash. I know this chip cannot debug during the STC, but why I cannot write into the flash yet.
I infer that it may drop-dead halt during the STC. I need to make my chip escape the STC so that I can download the new program and continue debugging.HELP!!

Some details about what I have done.
I use HCG software to create the program of STC.But this program just make STC run in startup, so I modify some codes to make STC run in MAIN.I konw I need to backup status of CPU and restore after STC.When I download my program into the chip second time, I get this"DBGEN is not asserted"and"Write failed (target is running) at Memory address 0xFFFFFF48".Also，I use SEGGER J-Flash ARM to connect the target，I get this"DBGEN is not asserted.Failed to connect". I have no idea to handle this problem.BTW I used IAR.

In my attachment, it consists of OUT file and screenshots of my codes.

4213.ABOUT TMS570ls3137CANNOT WRITE IN FLASH.rar

  • 0
    TI__Mastermind 22715 points
    Would you please use a scope to monitor the nRST pin? A CPU reset (nRST) is generated after STC test. If your software does not check if the reset is caused by STC, the STC will be run repeatedly and CPU is getting reset repeatedly. Therefore, you will not be able to connect to target (CPU).

    If the above is true, you should see nRST pin toggling. You can try the following method to connect to target.

    (1) hold nRST pin low.
    (2) simultaneously, release the nRST pin and click "connect to target" on debugger.

    The purpose of doing so is to halt the CPU before STC is started.

    To prevent this problem from happening again. I would suggest to replace the "b c_int00" instruction at address 0x0 by " b #-8". With this change, CPU will loop around address 0x0 after reset. You can use debugger to fully control the execution from the very beginning.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Prodigy 200 points

    First of all，thank you very much.

    I solved this problem by what you suggested to do.

    Then, I have a little confusion about what you told at last. --"I would suggest to replace the "b c_int00" instruction at address 0x0 by " b #-8""

    Can you explain how to configure it in the option much clearer .

    And I used IAR Compiler, I set the entry at "_c_int00" before.

    I do not know why use"b #-8" and what does it meaning?

    Thanks and regards,

    Cyrus

  • 0 in reply to user4267432
    TI__Mastermind 22715 points
    CPU starts to execute from address 0x0 after reset is released. When you "connect to target" (CPU is halted , the application code in flash has been executed for long time. If there is error in your code, you may run into tow types of issues.

    (1) Not able to connect to the target again as you already observed.
    (2) The failure observation is not consistent when you "connect to target" each time because CPU is halted at different point of execution.

    The instruction " b#-8" will force CPU to go back to the same address. With this instruction at address 0x0, you will see PC is stuck at address 0x0 after you "connect to target". Everything on this device will be at default. Then you can use debugger to fully control the execution. I think it a very useful method in the development. You will need to change it back to "b c_int00" after the debugging is done.

    Thanks and regards,

    Zhaohong