• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 875 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Non-optimal number of wait-states set by ROM_SysCtlClockFreqSet in a XM4C1294NCPDT revision 2 part?

Chester Gillon
Guru 92251 points
Other Parts Discussed in Thread: TM4C1294NCPDT

Calling the following in a XM4C1294NCPDT revision 2 part:

    freq = ROM_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                                   SYSCTL_OSC_MAIN |
                                   SYSCTL_USE_PLL |
                                   SYSCTL_CFG_VCO_480), 120000000);

Results in SYSCTL_MEMTIM0 being set to:

i.e. EWS and FWS have been set to 6 wait-states.

According to Table 5-12. MEMTIM0 Register Configuration versus Frequency in the TM4C1294NCPDT datasheet  DS-TM4C1294NCPDT-15863.2743 SPMS433B dated June 2014 with a 120MHz CPU frequency the optimum value of FWS/EWS is 5 wait-states, not 6 wait-states:

I think this has occurred because the MEMTIM0 Register Configuration versus Frequency table in the datasheet got changed. The revision history for the 15863.2743 revision data sheet says:

Updated table "MEMTIM0 Register Configuration vs. Frequency" with lower wait states, and improved performance values.
Looking at first issue data sheet DS-TM4C129XNCZAD-SPMS397 from October 2013 shows a FSW/EWS wait-state value of 6 was recommended for a 120MHz CPU frequency:

My question is does the ROM_SysCtlClockFreqSet need to be updated to match the MEMTIM0 Register Configuration versus Frequency table in the latest datasheet dated June 2014?

My test was with a XM4C1294NCPDT revision 2 part, not sure if the later revision 3 has a modified ROM_SysCtlClockFreqSet. Also, as a work-around the flash based SysCtlClockFreqSet() from TivaWare 2.1.0.12573 does set FWS/EWS to 5 when a 120MHz CPU frequency is selected.

  • 0
    Guru 117855 points

    @Chester,

    May I applaud (first) your superbly thought/crafted subject/title and (second) the logic & detail embodied w/in your neat investigative report.  Well done - I'd wager (with you) on your analysis/conclusion...

    Might your move from the ROM to FLASH version of that function (and then re-test) build definitive support for your finding?  [edit]  Alas - bottom line - your post - confirms your use of Flash and that it (indeed) escapes this extra wait-state...

  • 0 in reply to cb1_mobile
    TI__Guru**** 244400 points
    Hello cb1, Chester,

    The Flash version of the function has a wait state of 5 for 120MHz which is the updated version in the data sheet. However a ROM fix may not be possible as it requires a version change of the device. Unless there is a strong compelling reason to have Rev-4 Silicon this may not be changed and has to be errata'ed out.

    Regards
    Amit