• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 415 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EMIF - TMS570LC4357

pavithra pavithra
Intellectual 870 points
Other Parts Discussed in Thread: TMS570LC4357

Hi TI,

In tms570lc4357 hdk 64Mbit SDRAM is available.

in the data sheet memory map, it is mentioned that 128MB of SDRAM and (16MB*3) Async RAM.

available address lines are 22.

so what is the maximum size of SDRAM & Async RAM that can be used.

thanks!

  • 0
    TI__Guru 68920 points
    pavithra,

    if you want to maximize the SDRAM size you need 2 SDRAM chips each in a x8 config for the x16 bit data bus of the TMS570.
    the HDK has only 1 chip.

    The way to answer the max size is to look at the TRM, and find the max # of row address, column address, and banks that the controller support. Then find the biggest SDRAM part that will work w. the EMIF. You can get this information from Table 21-13. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM for example. The SDRAM you pick needs to be supported by one of the entries in this table.

    Similar algorithm can be used to figure out the max async memory size based on the information in 21.2.6 Asynchronous Controller and Interface, but it's easier because the address lines are not multiplexed row/column like they are on the SDRAM interface.