Flushing/clearing UART FIFO

A quick search through the datasheet UART chapter only revealed notes of flushing the transmit FIFO (by disabling & re-enabling the FIFO), so I'd wager that the only way to flush the receive FIFO is to just read bytes off it until it is empty. Or it could be that the receive FIFO is also flushed with the transmit FIFO - you'll need to experiment.

Veikko Immonen said:

flushing the transmit FIFO (by disabling & re-enabling the FIFO

Poster Veikko offers what appears to be a worthwhile suggestion - but does not (fully) detail the "how."

Simple, "disable/re-enable" seems a bit too "gentle" to this reporter.

Suspect that poster seeks, "quick/dirty/easy" method - might a, "UART Peripheral Reset" (targeting just your specified UART) prove more comprehensive - thus more effective?

As Veikko suggests - experimentation seems "best bet" until vendor staff (armed w/the always delightful, "insider info") return from hiatus...

Hello Ahmed,

Flush of the RX FIFO is possible by reading the junk data out or by reset of the peripheral instance

Regards
Amit

cb1_mobile said:

"UART Peripheral Reset" (targeting just your specified UART) prove more comprehensive

Ahem - is that not what (this reporter) earlier reasoned?   Surely green (verify) ink should flow...

Hi Amit, i can not distinguish between junk and useful data. I only know when will I receive the useful data so I need to reset the peripheral before reading. Can you tell me how can I reset UART for portC pin 4,5 ? When I initialize it before reading I always find the stale data !

Hi Amit, this is my issue, enable/disable is not solving the problem. I need to know the command to clear the RX FIFO

Hello Ahmed,

If you know when the useful data is arriving then first you would need to understand the cause for a junk data to come. Once that is established, one way is to shut off the Receiver during the junk time frame by disabling the RXEN bit in UARTCTLH register and enable it when the expected time frame for the "useful" data comes.

Regards
Amit

Hi Amit, I am communicating with RF circuit which sometimes gives me random message with different byte length. I check that data and can know that it is not the wanted one. So, I need to clear the UART FIFO to be able to read again and check if it is the wanted data. The problem is that I can not know the length of the received data so I prefer to clear the buffer every time. So it will be helpful to know what bit in register need to be set/cleared to clear the FIFO or any other way.

Thanks Amid for your help

Ahmed

Hello Ahmed,

The solution to such a situation would be to read and flush the FIFO. Assume that when if the FIFO had a reset function to clear the FIFO and a valid data was just written, then the reset would have cleared a valid data as well.

Regards
Amit

Hi Amit, no, this will not happen. I send a command for the RF to send me the useful data. The problem is that between two commands junk data may arrive and take place in the buffer. So when I read the FIFO, I found the junk data. I would like to clear the FIFO, send the command to the RF circuit, read the FIFO. In this case I am sure that the data bytes in the FIFO are my useful data only.

Ahmed

Hello Ahmed,

So in such a deterministic case, after the useful data has been read either of the two can be done

1. Set a flag stating all valid data is read and if the UART FIFO has data then read it unconditionally till the next command is not sent
2. On receiving the valid data, disable the receiver till the next command has to be sent. At that time read the FIFO if any junk data has come before the expected data.

Regards
Amit

Pardon but (exclusive) use of software seems to overly complicate.

Our group past encountered a similar situation. (invalid data arriving @ random intervals)   Amit (here) directs that the UART be disabled - then re-enabled - just prior to the "next command" is to be sent.   In our case - we achieved that same effect via the toggle of a GPIO - which blocked the data-flow into UART_RX - and proved both far faster and less cumbersome than an, "all software, peripheral impacting" alternative.

We note that this thread has (only) one (errant) "suggested Answer" highlight  - earlier (now verified) answer - from this reporter - remains uncredited/unmarked.   That's not right...

Hello cb1,

There are indeed multiple ways to do so, just suggesting a way (option 1) we have used as well. The more options that are given to the poster better they can evaluate as per the system they have implemented.

Regards
Amit

Amit Ashara said:

There are indeed multiple ways to do so...

Hi Amit,

Indeed - there are - but does the, "Disable" of UART prevent the arrival of "illegal/invalid" data @ UART_RX from (still) triggering an (now unwanted) interrupt(s)?   This was our past finding - and why we disabled via our level shifter.   (it is possible that we did this on another's M4 - our "escape" of interrupts dictated that we block UART input...)

Thanks Amit, it is a good idea. I will modify the code as your second suggestion. So, I will read the FIFO if any junk data has come, then I will send my command for the RF circuit and receive the expected data.  I will use a loop up to 16 to read NonBlocking UART data. An example 

////////////////////////////

for(int i=0; i<16; i++)

{

InJunk=UART_InCharNonBlocking();     //use non blocking not to stop the code at waiting forever in case there is no junk data.

}

//Send the command for RF circuit 

//Read data from RF circuit

//////////////////////////

Regards,

Ahmed