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EPI -FPGA interface IN TIVAC1294

Other Parts Discussed in Thread: TM4C1294NCPDT

Hello,

I am trying to get data from FPGA .I was able to read data.Now my requirement is FPGA will give interrupt and then i have to read data i made a sample code choose GPIO_PK4_EPI0S32 as interrupt pin.I am attaching my code ,plese help me in diasbling  interrupt and reading data from FPGA

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "inc/hw_epi.h"
#include "inc/hw_gpio.h"
#include <driverlib/gpio.h>
#include "driverlib/epi.h"
#include "driverlib/flash.h"
#include "driverlib/interrupt.h"
#include "driverlib/debug.h"
#include "driverlib/sysctl.h"
#include "driverlib/systick.h"
#include "driverlib/timer.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/pin_map.h"
#include "utils/locator.h"
#include "utils/lwiplib.h"
#include "utils/uartstdio.h"
#include "driverlib/uart.h"
#include "utils/ustdlib.h"
#include "drivers/pinout.h"
//#include "inc/tm4c1294ncpdt.h"
#include "io.h"
#include "cgifuncs.h"
#include "lwip/inet.h"


//*****************************************************************************
//
// Defines for setting up the system clock.
//
//*****************************************************************************
#define SYSTICKHZ 100
#define SYSTICKMS (1000 / SYSTICKHZ)

//*****************************************************************************
//
// Interrupt priority definitions. The top 3 bits of these values are
// significant with lower values indicating higher priority interrupts.
//
//*****************************************************************************
#define SYSTICK_INT_PRIORITY 0x80
#define ETHERNET_INT_PRIORITY 0xC0

////////////////////////////////////////////////////////////////////////////////////////
uint32_t sourceaddr, netmask,gateway;
struct ip_addr udpDestIpAddr;
//*****************************************************************************

#define FLAG_TICK 0
static volatile unsigned long g_ulFlags;

//*****************************************************************************
//
// External Application references.
//
//*****************************************************************************
extern void udp_init(void);

//*****************************************************************************
//
// SSI tag indices for each entry in the g_pcSSITags array.
//
//*****************************************************************************
#define SSI_INDEX_LEDSTATE 0
#define SSI_INDEX_FORMVARS 1
#define SSI_INDEX_SPEED 2

//*****************************************************************************
#define NUM_CONFIG_SSI_TAGS (sizeof(g_pcConfigSSITags) / sizeof (char *))

//*****************************************************************************

// CGI URI indices for each entry in the g_psConfigCGIURIs array.
//
//*****************************************************************************
#define CGI_INDEX_CONTROL 0
#define CGI_INDEX_TEXT 1

//*****************************************************************************
//
// The number of individual CGI URIs that are configured for this system.
//
//*****************************************************************************
#define NUM_CONFIG_CGI_URIS (sizeof(g_psConfigCGIURIs) / sizeof(tCGI))

//*****************************************************************************
//
// The file sent back to the browser by default following completion of any
// of our CGI handlers. Each individual handler returns the URI of the page
// to load in response to it being called.
//
//*****************************************************************************
#define DEFAULT_CGI_RESPONSE "/io_cgi.ssi"


// The current IP address.
//
//*****************************************************************************
uint32_t g_ui32IPAddress;

//*****************************************************************************
//
// The system clock frequency. Used by the SD card driver.
//
//*****************************************************************************
uint32_t g_ui32SysClock;
uint32_t g_ui32IntMode;

///////////////////////////////////////////////////

struct udp_pcb *my_pcb;
struct pbuf* pbuf1;
char buf [120];

char *g_pusEPIFPGA;
unsigned long index;
char *datasram;
int i=0;
unsigned short *cptr;
unsigned char cval;
volatile uint32_t g_ui32GPIOA;
////////////**************sdram
//char *cptr = (char *)0x20000500;

//*****************************************************************************
//
// The error routine that is called if the driver library encounters an error.
//
//*****************************************************************************
#ifdef DEBUG
void
__error__(char *pcFilename, uint32_t ui32Line)
{
}
#endif

////////////**********************************8///////////////////////////
/*void GPIOPinTypeEPI(uint32_t ui32Port,uint8_t ui8Pins)
{
// Check the arguments.
ASSERT(GPIOBaseValid(ui32Port));

// Make the pin(s) be peripheral controlled.
GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);

// Set the pad(s) for standard push-pull operation.
GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
}
*/

//*****************************************************************************
//
// The interrupt handler for the SysTick interrupt.
//
//*****************************************************************************
void
SysTickIntHandler(void)
{
//
// Call the lwIP timer handler.
//
lwIPTimer(SYSTICKMS);
}
///////////////////////////////////////////////////////////////////
void GPIOAIntHandler(void)
{


// Clear the GPIO interrupt.
GPIOIntClear(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);


}

void EPI_Init(void)
{
// Enable EPI0.
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//Configure EPIO
EPIDividerSet(EPI0_BASE, 1);
EPIModeSet(EPI0_BASE, EPI_MODE_HB16);
EPIConfigHB16Set(EPI0_BASE,(EPI_HB16_MODE_SRAM | EPI_HB16_WRWAIT_1 |EPI_HB16_RDWAIT_1 | EPI_HB16_WORD_ACCESS), 0);
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_BASE_C | EPI_ADDR_PER_SIZE_256B);////0xC0000000

//EPIFIFOConfig(EPI0_BASE, EPI_FIFO_CONFIG_TX_EMPTY | EPI_FIFO_CONFIG_RX_1_4);

// Configure GPIO
GPIOPinConfigure(GPIO_PB3_EPI0S28); //RD
GPIOPinConfigure(GPIO_PP2_EPI0S29); //WR

GPIOPinConfigure(GPIO_PK0_EPI0S0); //D0
GPIOPinConfigure(GPIO_PK1_EPI0S1); //D1
GPIOPinConfigure(GPIO_PK2_EPI0S2); //D2
GPIOPinConfigure(GPIO_PK3_EPI0S3); //D3
GPIOPinConfigure(GPIO_PC7_EPI0S4); //D4
GPIOPinConfigure(GPIO_PC6_EPI0S5); //D5
GPIOPinConfigure(GPIO_PC5_EPI0S6); //D6
GPIOPinConfigure(GPIO_PC4_EPI0S7); //D7
GPIOPinConfigure(GPIO_PA6_EPI0S8); //D8
GPIOPinConfigure(GPIO_PA7_EPI0S9); //D9
GPIOPinConfigure(GPIO_PG1_EPI0S10); //D10
GPIOPinConfigure(GPIO_PG0_EPI0S11); //D11
GPIOPinConfigure(GPIO_PM3_EPI0S12); //D12
GPIOPinConfigure(GPIO_PM2_EPI0S13); //D13
GPIOPinConfigure(GPIO_PM1_EPI0S14); //D14
GPIOPinConfigure(GPIO_PM0_EPI0S15); //D15

GPIOPinConfigure(GPIO_PL0_EPI0S16); //A0
GPIOPinConfigure(GPIO_PL1_EPI0S17); //A1
GPIOPinConfigure(GPIO_PL2_EPI0S18); //A2
GPIOPinConfigure(GPIO_PL3_EPI0S19); //A3
GPIOPinConfigure(GPIO_PQ0_EPI0S20); //A4
GPIOPinConfigure(GPIO_PQ1_EPI0S21); //A5
GPIOPinConfigure(GPIO_PQ2_EPI0S22); //A6
GPIOPinConfigure(GPIO_PQ3_EPI0S23); //A7
GPIOPinConfigure(GPIO_PK7_EPI0S24); //A8
GPIOPinConfigure(GPIO_PK6_EPI0S25); //A9
GPIOPinConfigure(GPIO_PL4_EPI0S26); //A10
GPIOPinConfigure(GPIO_PB2_EPI0S27); //A11

GPIOPinConfigure(GPIO_PP3_EPI0S30); //CHIP SELECT
GPIOPinConfigure(GPIO_PK5_EPI0S31); //CLK
GPIOPinConfigure(GPIO_PK4_EPI0S32); //IRDY
GPIOPinConfigure(GPIO_PN5_EPI0S35); //CRE

GPIOPinTypeEPI(GPIO_PORTA_BASE, 0xC0);
GPIOPinTypeEPI(GPIO_PORTB_BASE, 0x0C);
GPIOPinTypeEPI(GPIO_PORTC_BASE, 0xF0);
GPIOPinTypeEPI(GPIO_PORTG_BASE, 0x03);
GPIOPinTypeEPI(GPIO_PORTK_BASE, 0xFF);
GPIOPinTypeEPI(GPIO_PORTL_BASE, 0x1F);
GPIOPinTypeEPI(GPIO_PORTM_BASE, 0x0F);
GPIOPinTypeEPI(GPIO_PORTN_BASE, 0x20);
GPIOPinTypeEPI(GPIO_PORTP_BASE, 0x0C);
GPIOPinTypeEPI(GPIO_PORTQ_BASE, 0x0F);

GPIOPadConfigSet (GPIO_PORTA_BASE, 0xC0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTB_BASE, 0x0C, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTC_BASE, 0xF0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTG_BASE, 0x03, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTK_BASE, 0xFF, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTL_BASE, 0x1F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTM_BASE, 0x0F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTN_BASE, 0x20, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTP_BASE, 0x0C, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet (GPIO_PORTQ_BASE, 0x0F, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIODirModeSet (GPIO_PORTA_BASE, 0xC0, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTB_BASE, 0x0C, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTC_BASE, 0xF0, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTG_BASE, 0x03, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTK_BASE, 0xFF, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTL_BASE, 0x1F, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTM_BASE, 0x0F, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTN_BASE, 0x20, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTP_BASE, 0x0C, GPIO_DIR_MODE_HW);
GPIODirModeSet (GPIO_PORTQ_BASE, 0x0F, GPIO_DIR_MODE_HW);

}


void fpga_read()
{

#if 0
char *temp;

datasram = ( char *)malloc(1456*sizeof( char));
temp = datasram;

g_pusEPIFPGA = (char*)0xC0000000;

for(i = 0;i<144;i++)
{
*datasram = g_pusEPIFPGA[index];
*datasram++;
}

datasram = temp;

free(datasram);
#endif

unsigned short *cptr;// = (unsigned char *)0xC0000000;
//cval = *cptr;
cptr = (unsigned short *)0xC0000000;
while(i<=127)
{

cval = *cptr;
printf("Address of var1 variable: %x\n", *cptr );
cptr = cptr++;
i++;
}

cptr = (unsigned short *)0xC0000024;
cval = *cptr;

cptr = (unsigned short *)0xC0000004;
cval = *cptr;
cptr++;
cptr = (unsigned short *)0xC0000005;
cval = *cptr;
cptr++;
cptr = (unsigned short *)0xC0000256;
cval = *cptr;
cptr++;


}

//*****************************************************************************
//
// The interrupt handler for the timer used to pace the animation.
//
//*****************************************************************************
void
AnimTimerIntHandler(void)
{
//
// Clear the timer interrupt.
//
MAP_TimerIntClear(TIMER2_BASE, TIMER_TIMA_TIMEOUT);

//
// Indicate that a timer interrupt has occurred.
//
HWREGBITW(&g_ulFlags, FLAG_TICK) = 1;
}

//*****************************************************************************
//
// Display an lwIP type IP Address.
//
//*****************************************************************************
void
DisplayIPAddress(uint32_t ui32Addr)
{
char pcBuf[16];

//
// Convert the IP Address into a string.
//
usprintf(pcBuf, "%d.%d.%d.%d", ui32Addr & 0xff, (ui32Addr >> 8) & 0xff,
(ui32Addr >> 16) & 0xff, (ui32Addr >> 24) & 0xff);

//
// Display the string.
//
UARTprintf(pcBuf);
}

//*****************************************************************************
//
// Required by lwIP library to support any host-related timer functions.
//
//*****************************************************************************
void
lwIPHostTimerHandler(void)
{
uint32_t ui32Idx, ui32NewIPAddress;

//
// Get the current IP address.
//
ui32NewIPAddress = lwIPLocalIPAddrGet();

//
// See if the IP address has changed.
//
if(ui32NewIPAddress != g_ui32IPAddress)
{
//
// See if there is an IP address assigned.
//
if(ui32NewIPAddress == 0xffffffff)
{
//
// Indicate that there is no link.
//
UARTprintf("Waiting for link.\n");
}
else if(ui32NewIPAddress == 0)
{
//
// There is no IP address, so indicate that the DHCP process is
// running.
//
UARTprintf("Waiting for IP address.\n");
}
else
{
//
// Display the new IP address.
//
UARTprintf("IP Address: ");
DisplayIPAddress(ui32NewIPAddress);


}

//
// Save the new IP address.
//
g_ui32IPAddress = ui32NewIPAddress;
}

//
// If there is not an IP address.
//
if((ui32NewIPAddress == 0) || (ui32NewIPAddress == 0xffffffff))
{
//
// Loop through the LED animation.
//

for(ui32Idx = 1; ui32Idx < 100; ui32Idx++) //was < 17
{

//
// Toggle the GPIO
//
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1,
(MAP_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_1) ^
GPIO_PIN_1));

SysCtlDelay(g_ui32SysClock/(ui32Idx << 1));

}
}
}


//*****************************************************************************
//
// The UART interrupt handler.
//
//*****************************************************************************
void
UARTIntHandler(void)
{
uint32_t ui32Status;

//
// Get the interrrupt status.
//
ui32Status = ROM_UARTIntStatus(UART0_BASE, true);

//
// Clear the asserted interrupts.
//
ROM_UARTIntClear(UART0_BASE, ui32Status);

//
// Loop while there are characters in the receive FIFO.
//
while(ROM_UARTCharsAvail(UART0_BASE))
{
//
// Read the next character from the UART and write it back to the UART.
//
ROM_UARTCharPutNonBlocking(UART0_BASE,
ROM_UARTCharGetNonBlocking(UART0_BASE));


}
}

//*****************************************************************************
//
// Send a string to the UART.
//
//*****************************************************************************
void
UARTSend(const uint8_t *pui8Buffer, uint32_t ui32Count)
{
//
// Loop while there are more characters to send.
//
while(ui32Count--)
{
//
// Write the next character to the UART.
//
ROM_UARTCharPutNonBlocking(UART0_BASE, *pui8Buffer++);
}
}


//*****************************************************************************
int main(void)

{

uint8_t pui8MACArray[8];

// Make sure the main oscillator is enabled because this is required by
// the PHY. The system must have a 25MHz crystal attached to the OSC
// pins. The SYSCTL_MOSC_HIGHFREQ parameter is used when the crystal

// frequency is 10MHz or higher.
//
SysCtlMOSCConfigSet(SYSCTL_MOSC_HIGHFREQ);

//
// Run from the PLL at 120 MHz.
//
g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
UARTStdioConfig(0, 115200, g_ui32SysClock);

/////Enable all GPIO BANKS////////////////////////////
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

//
// Configure the device pins.
//
PinoutSet(true, false);

//
// Configure debug port for internal use.
//
UARTStdioConfig(0, 115200, g_ui32SysClock);

//
// Clear the terminal and print a banner.
//
UARTprintf("\033[2J\033[H");
UARTprintf("Ethernet IO Example\n\n");

//
// Configure SysTick for a periodic interrupt.
//
MAP_SysTickPeriodSet(g_ui32SysClock / SYSTICKHZ);
MAP_SysTickEnable();
MAP_SysTickIntEnable();

GPIOPinConfigure(GPIO_PK4_EPI0S32);//irdy
GPIOPinTypeGPIOInput(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);
GPIOIntTypeSet(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32, GPIO_FALLING_EDGE );
GPIOIntEnable(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);
IntEnable(INT_GPIOA);

// Enable interrupts to the processor.
//
ROM_IntMasterEnable();
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

//
// Enable interrupts to the processor.
//


EPI_Init();
fpga_read();


//
// Convert the 24/24 split MAC address from NV ram into a 32/16 split
// MAC address needed to program the hardware registers, then program
// the MAC address into the Ethernet Controller registers.
//
pui8MACArray[0] = 0x01;
pui8MACArray[1] = 0x02;
pui8MACArray[2] = 0x03;
pui8MACArray[3] = 0x01;
pui8MACArray[4] = 0x02;
pui8MACArray[5] = 0x03;

//
// Initialze the lwIP library, using DHCP.
sourceaddr=inet_addr("28.1.17.172");
netmask=inet_addr("0.0.255.255");
gateway=inet_addr("3.0.17.172");

lwIPInit(g_ui32SysClock,pui8MACArray,sourceaddr,netmask,gateway,IPADDR_USE_STATIC);

LocatorInit();
LocatorMACAddrSet(pui8MACArray);
// ***************************uart//////////////
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

//
// Configure the UART for 115,200, 8-N-1 operation.
//
ROM_UARTConfigSetExpClk(UART0_BASE, g_ui32SysClock, 115200,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));

//
// Enable the UART interrupt.

//
ROM_IntEnable(INT_UART0);
ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);


//
// Prompt for text to be entered.
//
UARTSend((uint8_t *)"hiiii hw r u tfrg ", 16);
UARTprintf("udp failed.\n");


/////////////*********************************
udp_init();

struct udp_pcb * mypcb;
mypcb = udp_new();
if (mypcb == NULL)
{
UARTprintf("udp failed.\n");
}
else
{
UARTprintf("udp up.\n");
}

if (udp_bind(mypcb, IP_ADDR_ANY, 8760) != ERR_OK)
{
UARTprintf("udp bind failed.\n");
}

//
// Set the interrupt priorities. We set the SysTick interrupt to a higher
// priority than the Ethernet interrupt to ensure that the file system
// tick is processed if SysTick occurs while the Ethernet handler is being
// processed. This is very likely since all the TCP/IP and HTTP work is
// done in the context of the Ethernet interrupt.
//
MAP_IntPrioritySet(INT_EMAC0, ETHERNET_INT_PRIORITY);
MAP_IntPrioritySet(FAULT_SYSTICK, SYSTICK_INT_PRIORITY);


// Initialize IO controls
//
io_init();

//
// Loop forever, processing the on-screen animation. All other work is
// done in the interrupt handlers.
//
while(1)
{
//
// Wait for a new tick to occur.
//
while(!g_ulFlags)
{
//
// Do nothing.
//
}
//
//
// Clear the flag now that we have seen it.
//
HWREGBITW(&g_ulFlags, FLAG_TICK) = 0;

//
// Toggle the GPIO
//
MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1,
(MAP_GPIOPinRead(GPIO_PORTN_BASE, GPIO_PIN_1) ^
GPIO_PIN_1));


//
// Transmit to UDP
//
//static int n = 0;
pbuf1 = pbuf_alloc(PBUF_TRANSPORT, 100, PBUF_RAM);
pbuf1->payload = cptr; //(void*)buf;
pbuf1->tot_len = 22; //data length
pbuf1->len = 20;


// *cptr = 'A'; cptr++;
//*cptr = 'A'; cptr++;
// *cptr = 'A'; cptr++;
// *cptr = 'A'; cptr++;
//*cptr = 'A'; cptr++;

// buf[0] = 'A';
//buf[1] = 'A';
//usprintf(&buf[4], " abcABC1230000000000 %d", n++);
IP4_ADDR(&udpDestIpAddr,172,17,2,30);
udp_sendto(mypcb, pbuf1,&udpDestIpAddr,1001);
pbuf_free(pbuf1);


}
}

Regards,

Krishnan

  • Hello Krishnan,

    Should IntDisable(INT_GPIOA) be sufficient in disabling the interrupt in the NVIC or using the GPIOIntDiable clear the Interrupt Mask in GPIO. Also a brief review of the code shows that the configuration of the GPIO has not been made correctly for PK4. Please refer to examples like LED for GPIO Configuration/

    Regards
    Amit
  • Hello,

    Thank you foe the message,

    My configurations was

    GPIOPinConfigure(GPIO_PK4_EPI0S32);//irdy
    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);
    GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);
    GPIOIntTypeSet(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32, GPIO_FALLING_EDGE );
    GPIOIntEnable(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);
    IntEnable(INT_GPIOA);

    What is the defference between these and ROM_


    ROM_GPIOIntEnable(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);
    ROM_IntEnable(INT_GPIOA);

    WHAT ARE THE OTHER CONFIGURATIONS REQUIRED ,

    Actual requirement is FPGA will give interrupt to controller when data is present and controller have to fetch data to its internel memoery.

    Any help is great.

    One more thing ,is 

    void GPIOAIntHandler(void)
    {


    // Clear the GPIO interrupt.
    GPIOIntClear(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);

    }

    enough to clear interrupt and read the fpga data.Like fpga will gave data and controller will be aware about data when interrupt is occuring.

    Please help me to solve.

    Regards,

    Krishnan

  • Hello Krishnan

    Using the ROM variant (when available) will save code space on the flash.
    Out of the following two line only the second one is needed. Other than that there is a gross error.

    GPIOPinConfigure(GPIO_PK4_EPI0S32);//irdy
    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE, GPIO_PK4_EPI0S32);

    When referring to the GPIO Pin in GPIO Mode the parameter GPIO_PK4_EPI0S32 must be GPIO_PIN_4

    Do remember to map the interrupt handler vector table for GPIO A!!!

    Regards
    Amjt
  • Hello Amit,

    Thank you for the message ,i made the necessary  changes

    GPIOPinTypeGPIOInput(GPIO_PORTK_BASE, GPIO_PIN_4);
    GPIOPadConfigSet(GPIO_PORTK_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA,GPIO_PIN_TYPE_STD);
    GPIOIntTypeSet(GPIO_PORTK_BASE, GPIO_PIN_4, GPIO_FALLING_EDGE );
    GPIOIntEnable(GPIO_PORTK_BASE, GPIO_PIN_4);
    IntEnable(INT_GPIOK);

    // Enable interrupts to the processor.
    //
    IntMasterEnable();

    and mapped ap the interrupt handler vector table for GPIO k to   "startup _ccs.c" and i and using 

    void GPIOKIntHandler(void)
    {


    // Clear the GPIO interrupt.
    GPIOIntClear(GPIO_PORTK_BASE, GPIO_PIN_4);
    {

    unsigned short *cptr;// = (unsigned char *)0xC0000000;
    //cval = *cptr;
    cptr = (unsigned short *)0xC0000000;

    while(i<=128)
    {

    cval = *cptr;
    printf("Address of var1 variable: %x\n", *cptr );
    cptr = cptr++;
    i++;
    } to read the data but here again i am facing difficulties....

    Thnaking for any suggestions ,please help........

    Regards,

    Krishnan

  • Hello Krishnan

    Is the interrupt working? Your post is not clear as to what is the problem now!!!

    Regards
    Amit
  • Sir,

    Thank you for helping me 

    We are getting interrupt now,i probed and seen,in fpga 2 buffers are used to send data,when one is full it will send then second so epi have to continuously raed data like disable one interrupt read data then disable second interrupt read data .........then packet it and send .Now i am looking for such an operation that epi have to read data from two fpga buffers one after another contineously. 

    Regards,

    Krishnan

  • Hello Krishnan,

    Since it is an FPGA, you can assign a static address for the FPGA. Reading the address will be managed by the FPGA where every read will cause the buffer to be switched.

    Regards
    Amit
  • Hello Amit,
    Thank you ,i will check it soon,but my doubt is after clearing the interrupt

    void GPIOKIntHandler(void)
    {


    // Clear the GPIO interrupt.
    GPIOIntClear(GPIO_PORTK_BASE, GPIO_PIN_4);
    {

    unsigned short *cptr;
    cptr = (unsigned short *)0xC0000000;

    while(i<=128)
    {


    printf("Address of var1 variable: %x\n", *cptr );
    cval = *cptr;
    cptr = cptr++;

    }
    }
    }
    like this i tried a code but not working.I am using epi sdram,hb16.
    Weather interrupt will be disabled before epi bus configuration or after the configuration.
    My code is not working also.My requirement is to contineously read the data

    Regards,
    Krishnan
  • Hello Krishnan,

    It depends whether in the main code you have enabled the interrupt before the configuration and the edge event occurs. To ensure that the sw acknowledges the right interrupt, enable it after the configuration of EPI and before enabling the interrupt in the NVIC, clear the interrupt status.

    On reading the data continuously, it is a function of the FPGA being able to understand the transaction.

    Regards
    Amit