how to configure for use with a IRDY?
Host-bus8 mode, ALE with Quad CSn Configuration. The duration of the signal WR (RD) 0,5-4mks ( slow device BU- 61580 ) . Access is determined by the length of the ready signal RDY.
#include <stdint.h>
#include "inc/tm4c129xnczad.h"
int
main(void)
{
volatile uint32_t ui32Loop;
volatile unsigned ud32, ux32, ua, ub, uc, ud, ue,uf,ug,uh,uj,uk,ul,um,un,up,uq,ur,us,ut;
int ii;
//
// Enable the GPIO port that is used for the on-board LED.
//
SYSCTL_RCGCGPIO_R = SYSCTL_RCGCGPIO_R14;
//
// Do a dummy read to insert a few cycles after enabling the peripheral.
//
ui32Loop = SYSCTL_RCGCGPIO_R;
//
// Enable the GPIO pin for the LED (PQ7). Set the direction as output, and
// enable the GPIO pin for digital function.
//
GPIO_PORTQ_DIR_R = 0x80;
GPIO_PORTQ_DEN_R = 0x80;
//Enable the EPI module using the RCGCEPI register
SYSCTL_RCGCEPI_R=SYSCTL_RCGCEPI_R0;
//Enable the clock to the appropriate GPIO module via the RCGCGPIO register
ud32=SYSCTL_RCGCGPIO_R ;
SYSCTL_RCGCGPIO_R =ud32|0x5ec7;
ud32=SYSCTL_RCGCGPIO_R ;
GPIO_PORTA_AHB_LOCK_R=0x4C4F434B;
GPIO_PORTB_AHB_LOCK_R=0x4C4F434B;
GPIO_PORTC_AHB_LOCK_R=0x4C4F434B;
GPIO_PORTG_AHB_LOCK_R=0x4C4F434B;
GPIO_PORTH_AHB_LOCK_R=0x4C4F434B;
GPIO_PORTK_LOCK_R=0x4C4F434B;
GPIO_PORTL_LOCK_R=0x4C4F434B;
GPIO_PORTM_LOCK_R=0x4C4F434B;
GPIO_PORTN_LOCK_R=0x4C4F434B;
GPIO_PORTQ_LOCK_R=0x4C4F434B;
//Set the GPIO AFSEL bits for the appropriate pins
GPIO_PORTA_AHB_AFSEL_R=GPIO_PORTA_AHB_AFSEL_R|0xc0;
GPIO_PORTB_AHB_AFSEL_R=GPIO_PORTB_AHB_AFSEL_R|0x0C;
GPIO_PORTC_AHB_AFSEL_R=GPIO_PORTC_AHB_AFSEL_R|0xF0;
GPIO_PORTG_AHB_AFSEL_R=GPIO_PORTG_AHB_AFSEL_R|0x03;
GPIO_PORTH_AHB_AFSEL_R=GPIO_PORTH_AHB_AFSEL_R|0x0F;
GPIO_PORTK_AFSEL_R =GPIO_PORTK_AFSEL_R |0xF0;
GPIO_PORTL_AFSEL_R=GPIO_PORTL_AFSEL_R|0x3F;
GPIO_PORTM_AFSEL_R=GPIO_PORTM_AFSEL_R|0x0F;
GPIO_PORTN_AFSEL_R=GPIO_PORTN_AFSEL_R|0x3C;
GPIO_PORTQ_AFSEL_R=GPIO_PORTQ_AFSEL_R|0x0F;
// Configure the GPIO current level and/or slew rate as specified for the mode selected
//Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate pins
GPIO_PORTA_AHB_PCTL_R =GPIO_PORTA_AHB_PCTL_R | 0xFF000000;
GPIO_PORTB_AHB_PCTL_R =(GPIO_PORTB_AHB_PCTL_R) | 0x0000FF00;
GPIO_PORTC_AHB_PCTL_R =(GPIO_PORTC_AHB_PCTL_R) | 0xFFFF0000;
GPIO_PORTG_AHB_PCTL_R =(GPIO_PORTG_AHB_PCTL_R) | 0x000000FF;
GPIO_PORTH_AHB_PCTL_R =(GPIO_PORTH_AHB_PCTL_R) | 0x0000FFFF;
GPIO_PORTK_PCTL_R =(GPIO_PORTK_PCTL_R) | 0xFFFF0000;
GPIO_PORTL_PCTL_R =(GPIO_PORTL_PCTL_R) | 0x00FFFFFF;
GPIO_PORTM_PCTL_R =(GPIO_PORTM_PCTL_R) | 0x0000FFFF;
GPIO_PORTN_PCTL_R =(GPIO_PORTN_PCTL_R) | 0x00FFFF00;
GPIO_PORTQ_PCTL_R =(GPIO_PORTQ_PCTL_R) | 0x0000FFFF;
// Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the
// MODE field in the EPI Configuration (EPICFG) register
EPI0_CFG_R=EPI0_CFG_R | EPI_CFG_BLKEN | EPI_CFG_MODE_HB8 ;
//Set the mode-specific details (if needed)
//using the appropriate mode configuration
//EPI Host Bus Configuration (EPIHBnCFGn) registers
//for the desired chip-select configuration.
EPI0_HB8CFG_R = EPI0_HB8CFG_R | EPI_HB8CFG_ALEHIGH | 0x18000000;// | EPI_HB8CFG_IRDYINV ;// ;// ;//| EPI_HB8CFG_WRWS_1 | EPI_HB8CFG_WRHIGH | EPI_HB8CFG_RDYEN | EPI_HB8CFG_IRDYINV ;
EPI0_HB8CFG2_R=EPI0_HB8CFG2_R | EPI_HB8CFG2_CSCFGEXT | EPI_HB8CFG2_CSCFG_DCS ;//| EPI_HB8CFG2_RDWS_3 ;
//Set the EPI Main Baud Rate (EPIBAUD) and EPI
//Main Baud Rate 2 (EPIBAUD2) register if
//the baud rate must be slower than the system clock
//rate
EPI0_BAUD_R=0x10001;
EPI0_BAUD2_R=0x10001;
//Configure the address mapping using the EPI Address Map (EPIADDRMAP) register
ud32= EPI0_ADDRMAP_R;
EPI0_ADDRMAP_R=EPI0_ADDRMAP_R | EPI_ADDRMAP_EPADR_HBQS | EPI_ADDRMAP_ERADR_HBQS;
ud32= EPI0_ADDRMAP_R;
ud32=0;
//
// Loop forever.
//
while(1)
{
for(ux32=0;ux32<=10;ux32++){
ud32=*((unsigned char*)(0x60000000+ux32));
for( ii=0;ii<999999;ii++){
ud32=ii;
};
}
}
}
