Unclear requirements for TMS570 initialization sequence

Hi Michael,

At a high-level, this section in the application note includes other steps that can be taken by the application to further test built-in diagnostic features on the MCU. The test for these additional features is not described in this application note and was deferred for inclusion in the future. For your specific questions, see explanations in the text below:

• 46. Verify that a memory protection unit (MPU) violation for all bus masters is flagged as an error to the ESM.
  • Bus masters are modules that can initiate a write or a read transaction. For example, on the TMS570LS12x/11x MCUs, the bus masters are the Cortex-R4F CPU, the DMA controller, the HTUx, the FTU and the EMAC modules. Of these bus masters, the CPU, the DMA, the HTUx and the FTU have dedicated built-in memory protection units that can be configured to prevent these bus masters from overwriting regions in memory. This requirement essentially means that you configure the MPU to prevent the bus master from writing to a certain memory region, and then you actually make the bus master write to that region to make sure that the MPU detects and indicates an access privilege fault.
• 51. Set up the MPU for the bus masters.
  • The initialization sequence described in the application note does not include setting up the MPU for each bus master. This is a recommended step for a safety application. Check the part's safety manual for more specific recommendation related to the MPU.
• 53. Configure the N2HET1-to-N2HET2 monitoring functionality.
  • Some terminals are intentionally shared between N2HET1 and N2HET2. This is done so that one N2HET can "see" what the other N2HET is outputting. For example, consider the ball T1 on TMS570LS1227. This terminal is shared between the N2HET1[7]/N2HET2[14]/EPWM7B functions. Now suppose that N2HET2 is outputting a PWM on this terminal as N2HET2[14]. The N2HET1 can have an input capture program that measures the period and duty cycle of the signal input on N2HET1[7]. This allows the application to ensure that all period and duty cycle updates for the output PWM are correctly done.
• 54. Configure desired access permissions for peripherals using the Peripheral Central Resource (PCR) controller registers. (-> Our bare metal application is running in privileged modes only)
  • In addition to the MPU for each bus master, the PCR also offers some additional protection for peripheral control registers and peripheral memories that are accessed through the PCR. You can enable registers to be written only in privileged mode of operation. That means that the CPU must be in a privileged mode to write to the selected register frame. The DMA cannot operate in privileged mode, so this offers protection against a DMA transaction accidentally overwriting a control register. During initialization, you can configure some registers to be writable only in privileged mode and then write to a register in user mode of operation. The application can ensure that an abort is generated in this case. Of course this does not help when your CPU is always operating in privileged mode (not recommended).

Regards,

Sunil