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TM4C123 AIN0 problem

Other Parts Discussed in Thread: TM4C123BH6PGE, TM4C123GH6PGE

Hi,

I am using 22 analog inputs on a TM4C123BH6PGE. My prototype board works perfectly. My production board, running the same code, has a problem.

The prototype board has chip marked....

980 YF    TM4C123B    H6PGEI    35AVELW    G4

The production board has chip marked....

980 YF    TM4C123B    H6PGEI    35AVENW   G4

I can't find out how to read the silicon revision on the chip.

I am using PE3 for AIN0, this is driven directly by an opamp which is buffering a pot. It appears that the voltage presented to this pin affects all the other adc channels as if the input multiplexer is not working properly. This happens even if I do not sample this channel. Cutting the track to this pin stops the problem happening, so it seems it is not a board error.

I can't find a reference to this in any of the errata, but may be I missed something?

Can anybody help please?

Thanks, Richard

I put these two lines at the top of each file. Is this right?...

#define PART_TM4C123GH6PGE
#define TARGET_IS_BLIZZARD_RA1

My ADC initialisation code is....

        ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOE);
        ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

        ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_7);        //ch20
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_6);        //ch21
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_5);        //ch8
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_4);        //ch9
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);        //ch0
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);        //ch1
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_1);        //ch2
        ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0);        //ch3

        ROM_ADCSequenceDisable(ADC0_BASE, 1);                                                    //disable sequence before we change it
        ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);                        //select processor (software) trigger
        ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, 0 | ADC_CTL_IE | ADC_CTL_END);
        ROM_ADCIntClear(ADC0_BASE, 3);                                                            //clear the interrupt status flag
        ROM_ADCSequenceEnable(ADC0_BASE, 3);                                                    //enable sequence

My ADC sampling function is....

unsigned long getADC0(unsigned long channel)        //channel is bit mask eg ADC_CTL_CH0
{
uint32_t ADC0_value[1];

    //ROM_ADCSequenceDisable(ADC0_BASE, 3);                  //disable sequence 3 before we change it; doesn't seem to be necessary
    ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, channel | ADC_CTL_IE | ADC_CTL_END);
    //ROM_ADCSequenceEnable(ADC0_BASE, 3);                   //enable

    ROM_ADCProcessorTrigger(ADC0_BASE, 3);                //trigger
    while(!ROM_ADCIntStatus(ADC0_BASE, 3, false))       //wait complete
    {
    }

    ROM_ADCIntClear(ADC0_BASE, 3);                        //clear the ADC interrupt flag
    ROM_ADCSequenceDataGet(ADC0_BASE, 3, ADC0_value);   //read ADC Value

    return ADC0_value[0];
}