This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Problem with IRQ's configured in DISPATCH mode.

Other Parts Discussed in Thread: HALCOGEN

The code generated using halcogen with IRQ's configured in dispatch mode,

My application runs in to Undefined mode on power-up but works fine in debug mode(Just i have to initiate a soft reset)  

Let me know if anyone facing similar issue.

For further information 

My interrupt Vectors:

resetEntry

b _c_int00


undefEntry
b undefEntry

svcEntry
b SvcHandler

prefetchEntry
b prefetchEntry

dataEntry
b dataEntry

reservedEntry
b phantomInterrupt

irqEntry
b irqDispatch

fiqEntry
ldr pc,[pc,#-0x1b0]

My Dispatcher code snippet  looks like this:

.arm

.sect ".text::irqDispatch"
.global irqDispatch
.armfunc irqDispatch

irqDispatch: .asmfunc
STMFD sp!, {r0-r3,r12,lr} ; store the user mode registers on irq-stack.
BL AppIrqHandler ; Jump to the exception handler, branch with link
MOV r3,#0...

.....

......

$EXIT:
LDMFD sp!,{r0-r3,r12,lr} ; Pop new user registers + return address(lr) from stack
SUBS pc,lr,#4 ; Load PC with lr-4 , this should carryout the switching

Thanks in advance.

  • Amit,

    Without a real code, it is difficult to debug what is going wrong.

    Here is an example on how to manage IRQ in Dispatch mode.

    This example assume that in HalcoGen the following is setup:

    I've added the following code in sys_vim.c

    /* USER CODE BEGIN (1) */
    void _irqDispatch(void)
    {
        uint16 vector_index;
        do
        {
         vector_index = vimREG->IRQINDEX;
         (*(vimRAM->ISR[vector_index]))();
        } while(vector_index !=0);
    }
    /* USER CODE END */

    My sys_intvecs.asm looks like:

    ;-------------------------------------------------------------------------------
    ; interrupt vectors
        .ref _irqDispatch

    resetEntry
            b   _c_int00
    undefEntry
            b   undefEntry
    svcEntry
            b   svcEntry
    prefetchEntry
            b   prefetchEntry
            b   _dabort
            b   phantomInterrupt
            b   _irqDispatch
            ldr pc,[pc,#-0x1b0]

    If you want to try this example, here is the full project.5086.TMS570LS0432_Interrupt_Dispatch.zip

  • Thank you Jean for the reply.

    The only difference in my code and the example you mentioned is i have written the IrqDispatch in assembly ....... i have attached the same for your reference.

    Let me know if you need any further information. Is it possible to have a online meeting? 

  • Amit,

    I did check your dispatcher.asm, unfortunately there is not a lot I can do.

    This code is mainly your context switch. The only interesting part is:

    irqDispatch: .asmfunc

       STMFD   sp!, {r0-r3,r12,lr}          ; store the user mode registers on irq-stack.

       BL      AppIrqHandler                ; Jump to the exception handler, branch with link

    Could you share your AppIrqHadler code.

    On power on reset, when your code crashes, can you trace back?
    LR should contain the address of the faulty instruction.

    We can setup a webex if you want, but I'm not sure what could be the outcome. What is your time zone?

  • Jean,

    Thanks for the reply

    My link register points to 0x00007292(Not 4 byte aligned ), but when i search the address in dis-assembly window i see the instructions are all 4 byte aligned ......

    Snippet from Dis-assembly window .

    0000728c: EA000013 B $C$L4
    81 _memInit_();
    $C$L1:
    00007290: EBFFFA04 BL $../Platform_Specific/source/HL_sys_core.asm:471:490$
    87 _coreInitRegisters_();
    00007294: EBFFF956 BL $../Platform_Specific/source/HL_sys_core.asm:14:77$
    93 _coreInitStackPointer_();

    Application irq handler code looks like this

    void AppIrqHandler(void)
    {

    U32 recv_irq = 0x00000000;

    recv_irq = vimREG->IRQINDEX;

    switch(recv_irq)
    {

    case (RTI_COMPARE0):
    {

    rtiCompare0Interrupt();

    break;
    }
    case (RTI_COMPARE1):
    {

    rtiCompare1Interrupt();

    break;
    }
    default:
    UnimplementedIsr();
    break;

    }

    }

    My time zone is GMT + 5:30, let me know your time zone too.... 

  • Amit,

    I assume the device you are using is either TMS570LC43xx or RM57xx. Can you confirm.

    Also, can you tell me in which mode do you compile your code? ARM, Thumb2 or mix mode.

    The CPU needs ARM mode for all exception. Without full visibility on your code, I don't know what else can be done.

    Anyway, I've send you a friend request so we can communicate via private email.

  • Dear Jean,

    The device is TMS570LC43XX, am compiling in 32 bit mode(--code_state=32)
  • Amit,

    Could you send me the linker command file you are using to link your code.
    I want to check something.