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tm4c123gxl, changing pwm duty cycle with respect to falling edge counting



Hello TI community;

Shot question: I want to create a signal pattern which is , one long pulse and 3000 short pulses. (Counting the number is importan.)

Long: I have been reading the data sheet for 1-2 weeks and made some researches but could not find exact answer. To achieve my goal, I "think" I need a pwm signal which alternates the duty cycle by its own pulse number. Well, I am planning to use sync mode to make transition of duty cycle without any overly short or long pulse. Let me explain by example, let's say, my frequency is constant, and initially my duty cycle is 20% and just after first falling edge, I want to change my duty cycle to 1%, since I use sync mode, It will wait to complete the cycle(counter reaches 0) and then updates. Then for 3000 pulses my duty cycle is 1%. Just after 3000th pulse's falling edge again my duty cycle will be updated to be 20%.

Questions

1) Is my approach correct or is there a more robust and faster way than using pwm module (pwm is ok but with another approach)?

2) If my approach is correct, then how to implement it, let's say how to count falling edge which is created by pwm module.

Any suggestion is appreciated,

Regards

  • Suspect we'll need Amit for this level of detail - but may I note 2 things - designed to assist?

    a) Often ARM MCUs reveal "issues" at PWM duty cycle "extremes." (we note this w/multiple ARM vendors) Your 1% duty is my concern.

    b) Might you escape the (above) PWM limitation via use of a standard, ARM Timer? If your MCU system clock is high enough - perhaps you can create that 1% duty via several "Timer ticks" - and then multiply that "Timer tick value" by 20 to yield the 20% duty cycle...

    You'd employ the 2nd half of a Timer - or a separate Timer - to "count" the number of generated pulses.  When the "max count" is reached - you'd either load new Timer values - or (likely faster) toggle a GPIO to switch externally to a different Timer output.
     
    I'm "blue-skying" this response - it may require two Timers - and clever (i.e. external or gate) HW to realize a "real world" MCU implementation.

    (we've done very similar to this w/FPGA - child's play there...)

  • Thanks for your response, so you are saying that extreme values of duty cycles may cause some problems and reliability issues. Also making updates on pwm duty cycle at high frequencies may not be feasible, right? Do you recommend me to employ a FPGA for this project? At least for edge detection and signal generating?
  • Semih TOK said:
    extreme values of duty cycles may cause some problems and reliability issues. Also making updates on pwm duty cycle at high frequencies may not be feasible, right? Do you recommend me to employ a FPGA

    Fast/furious new questions fly...   Yes - May not be (that's a hedge) - Not yet (employ FPGA)

    If we can get away w/MCU's Timer - and perhaps simple gate to facilitate switch-over between two Timers - we may avoid the FPGA.   (FPGA is "sure-thing" - but MCU is more flexible, cost/size saver - thus its appeal.

    Timer method should escape the PWM Generator's issue - should not be too hard nor demanding to configure & test...

  • Hello cb1, Semih,

    At System Clock of 80MHz the 1% is very much available. The Sync update mechanism will indeed achieve the manner in which the user wants to update the DC as well. It should be set not to Immediate update mode but to Updated on Load condition.

    Regards
    Amit