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interrupt.c in driverlib

Gary Coakley
Prodigy 170 points
Other Parts Discussed in Thread: TM4C1294NCZAD

Using the driverlib for Tiva TM4C1294NCZAD, I see the following lines of code starting at line 69:

//*****************************************************************************

//

// This is a mapping between interrupt number and the register that contains

// the priority encoding for that interrupt.

//

//*****************************************************************************

static const uint32_t g_pui32Regs[] =

{

   0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3,

     NVIC_PRI0, NVIC_PRI1,

   NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,

   NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,

   NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,

   NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,

   NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,

   NVIC_PRI32, NVIC_PRI33, NVIC_PRI34

};

 

I believe that the line immediately following the left brace should NOT be there since it offsets all of the priority addresses.  Has anyone else seen this or has it been fixed already or am I all wet?

Thanks,

Gary

  • 0
    TI__Guru**** 244400 points
    Hello Gary,

    I am seeing the same as in TivaWare 2.1.0-12573

    static const uint32_t g_pui32Regs[] =
    {
    0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
    NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
    NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
    NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
    NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
    NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
    NVIC_PRI32, NVIC_PRI33, NVIC_PRI34
    };

    Regards
    Amit
  • 0
    Expert 2415 points

    If you take a look at how that array is later used (IntPrioritySet/Get), you should see that there is no problem. The structure of that array is not intended as a direct "window" to the register address space, it's just a mapping of interrupt numbers (which become indexes to that array when properly bitshifted) to register addresses. In register space, the NVIC_SYS_PRI* registers are actually after the NVIC_PRI* registers, with quite a few addresses inbetween...

    I wonder if you're thinking this is like the *regs structs in the C2000 side?

  • 0 in reply to Veikko Immonen
    Prodigy 170 points


    So, this code:

     

     

     

    void

    IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority)

    {

       uint32_t ui32Temp;

     

       //

       // Check the arguments.

       //

       ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));

     

       //

       // Set the interrupt priority.

       //

       ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);

       ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));

       ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));

       HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;

    }

     

    is supposed to set PRI1 for theSSI0 int? ( #23 )?

    Gary

  • 0 in reply to Gary Coakley
    Expert 2415 points
    As far as my in-head compiler/debugger is correct, yes, it does access NVIC_PRI1 when ui32Interrupt is 23. What makes you think it doesn't?
  • 0 in reply to Gary Coakley
    TI__Guru**** 244400 points
    Hello Gary,

    Yes, it is. The Interrupts 0-15 are mapped for Exception Types and they feed to the SYS_PRI registers. The interrupts 16 onwards (where SSI3 lies) are then mapped to the Interrupt section of the Cortex M4 for which PRI0-31 are the priority registers.

    Regards
    Amit