two questions about the STC of TMS570ls3137

Hello user4267432;

First, the concept of intervals closely maps to a test vector approach. In other words, each interval is a separate test that is testing different areas of the core. With this said, it is important to know that the tests are designed to test the core at gate levels using the microcode stored in the STC ROM. Each separate interval executed will gain coverage of a percentage of the overall gates. For example if you execute interval 0 repeatedly, you will only get 62.13% coverage and never more. If you add the second interval, you will get approximately an additional 8% coverage, a third will give + approx. 4.4%, and you will only achieve the full 90.21% coverage when all 24 intervals have been executed.

With this in mind, one approach to performing the CPU BIST is to execute a few intervals periodically in your application. For example, if you have a 500us main loop, you would execute 8 intervals continuing from the last executed interval in the next loop until all 24 are executed. This means it would take 3 iterations of your main loop before you have the full capability of the coverage but you would have this during the active execution of the application. It is key to understand that during the CPU BIST, the CPU is completely unavailable to the application so you must plan the number of intervals in accordance with your applications ability to handle this period of unresponsiveness.

Finally, the STCGC0 register has the field that determines how many intervals are executed for each loop/instantiation as you mentioned in your post. As long as you set the RS_CNT field to continue STC run from previous interval, you will always get a continuation. You can check this by looking at the interval count given in STCCICR which you will see increment for each interval execution and which will allow you to monitor the level of coverage you have achieved so far.