TMS570LC4357 Flash lock and control register

Hello Hercules support team,

1. In the TMS570LC4357 device TRM SPNU563.pdf (Version May 2014) , it states that the Flash control register FSM_WR_ENA (Section 7.11.30) must be first set to 0x5 before write to any other addresses between 0xFFF87200 and 0xFFF872FF. I have tested and seen that the register EEPROM_CONFIG (offset 0x2B8) can be written without writing FSM_WR_ENA to 0x5 (in my test it has the default value 0x2).
   
   Please check if the behavior described above is OK or the TRM should be updated.
2. Moreover, the TRM also states that the register FLOCK must be set to 0xAA55 before writing the register FEDACCTRL1. But in my test, FLOCK is 0x55AA, the FEDACTRL1 can be written.
   
   Please check if the behavior described above is OK or the TRM should be updated.

      3. In the code from some driver provider, I see that the register FSM_EXECUTE (offset 0x2B4) was updated. But this register is not documented in the TRM. Could you please provide the register description?

Thanks and best regards,

Libo