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ADC Sampling frequency calculation in TMS570LS3137 Microcontroller

satya sudhir sure
Intellectual 405 points

Hi,

I configured ADC as per below specified values but there is a difference between the configured sampling frequency(group cycle time) and calculated group cycle time.

ADC Device: ADC1;

Group : Group1 only;

Channels : Channel 0, Channel 1 and Channel 2;

VCLK : 80 Mhz;

ADC Clock Prescaler (PS) : 4;

Group1 Acquisition Time (G1 ACQ) : 2;

Group1 sample cap discharge cycles (G1 SAMP DIS CYC) : 3;

ADC Trigger : Software Trigger

Conversion Mode : Continuous

Calculated Sampling frequency (Group Cycle Time) is 266.67 KHz.

Measured Sampling frequency by toggling GPIO is 249.24 KHz

Please clarify the reason for difference b/w Calculated & Measured sampling frequencies. Also let us know if any delays to be added.

Kindly, provide the solution at the earliest.

Thanks & Regards,

Satya Sudhir Sure

  • 0
    TI__Mastermind 49120 points
    Satya,

    There are also 4 VCLK cycles between the end-of-conversion for one group sequence to the start of sampling of the first channel in the next group sequence. Also, which event are you using to toggle the GIO pin? Are you polling any particular status flag?

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Intellectual 405 points

    Hi,

    As per Earlier calculations,

    Sampling frequency (Group Cycle Time) is 266.67 KHz.

     

    If we consider 4 VCLK cycles delay for each conversion,

    then calculated Sampling frequency for Group-1 (3 Channels) would be 256.41 KHz.

    Measured Sampling frequency by toggling GPIO is 249.24 KHz.

    Still there is a difference between the calculated and measured sampling frequencies.

     

    Moreover, GPIO toggling was done using a DMA Channel & trigger to DMA is ADC End of Conversion after 3 Channels in Group-1.

    Please clarify at the earliest.

     

    Thanks & Regards,

    Satya Sudhir

     

  • 0 in reply to satya sudhir sure
    TI__Mastermind 49120 points
    Hi,

    Do you have any other DMA channel being used? If so, this could cause some variability in when the DMA request is addressed.

    Can you post the actual snapshot of the ADC control registers, specifically those related to the timing: prescaler/acquisition/sample-cap-discharge?

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    TI__Genius 11645 points
    Hi,

    Pls let us know if your issue is solved ? If not then the details requested by sunil. Thanks.