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TM4C1294NCPDT : program execution from the external SDRAM

Michi Yama
Guru 10030 points

Hi,

I have one question regarding TM4C1294.

I know that Cortex-M4 core does not have the internal cache. TM4C1249 also is the same.

If I place my execution code in the external SDRAM, the SDRAM access happens each instruction fetch.

This means that program execution is too slow.

Is my understanding right?

Please advise me.

Best regards,

Michi

  • 0
    TI__Guru**** 244400 points
    Hello Michi,

    The SDRAM fetch may not happen every clock cycle, since the Row and Column needs to be opened before a read may be performed, and that is why Program Fetches would be slow. This is true for all devices with external SDRAM for code execution unless a cache is implemented at memory controller.

    Regards
    Amit