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How to continously send data to AD5754 D/A converter with TM4C1924XL?

Nicolas Göddel
Intellectual 795 points

Hi,

I have a Tiva C Series Connected Launchpad TM4C1294XL and I have the AD5754 D/A converter connected to it.

I am able to send data to it over SSI2. But now I want to send a whole block of data (say 512 16 Bit samples to it). The problem is that the AD5754 needs the following cycle for each sample:

  • Set SYNC to low.
  • Send channel number over SPI (8 Bit)
  • Send channel value over SPI (16 Bit)
  • Set SYNC to high.
  • Send other channel?
  • Trigger LDAC to update the analogous outputs.

Before you trigger LDAC you may first send all four channel values to the device and then trigger their outputs at the same time.

Theoretically (according to the datasheet) I am able to update all four channels 268961 times a second. But if I do this the CPU has no time to do other stuff like networking or reading/writing from/to an SD card. So I thought I could use µDMA for that purpose. But how can I teach my µC to send this data block in smaller 24 Bits blocks and set SYNC high and then low between these blocks?

I could use two µDMA channels. One of them sends the 24 Bit data blocks with an 8 Bit "gap" (null byte) between them. The other µDMA channel sets SYNC to high while the first one sends the 8 Bit gap. With a third µDMA channel I also would be able to trigger LDAC after 4 values were sent to the AD5754.

Do you have any ideas?

  • 0
    TI__Guru**** 244400 points
    Hello Nicolas,

    What you are looking for is Peripheral Scatter Gather or Memory Scatter Gather with 6 task elements for a single channel. Since the SPI in legacy mode can only support upto 16 bits, I would have it configured in 8-bit mode.
    1. First Task to write to a GPIO to make it low (SYNC).
    2. Second task transfer 3 bytes (8-bits x 3 = 24-bits).
    3. Third task copies data from one SRAM location to another such that it is equivalent to total transmission time for 24-bits
    4. Fourth task make the GPIO High (SYNC)
    5. Fifth task make the LDAC low
    6. Sixth task make the LDAC high.

    Note that the uDMA does not know anything about the transfer being complete (step 2), so the mechanism to have delay in step-3 is important. Since t10=130ns is required another delay loop may be needed.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 795 points

    That sounds nice. Is there anywhere an example which shows me how to correctly use this Peripheral Scatter Gather or Memory Scatter Gather mode?

    Edit: Is it possible to wait for the SPI transaction complete flag in step 3 instead of copying data from one SRAM location to another? And can I use a specific execution time for DMA?

  • 0 in reply to Nicolas Göddel
    TI__Guru**** 244400 points
    Hello Nicolas

    PSG or MSG is one of the most complicated mode and very rarely used as delay is unpredictable especially for timing critical applications. In this case it would be the other way around as a minimum delay needs to added.

    The uDMA only sees a trigger and transfers and does not do wait for a flag. Thus the copy mechanism. Alternatively, you can use a timer to time the event, but then CPU will spend more time with the timer than doing anything else. That approach will however make some time for the CPU.

    Regards
    Amit