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TMS570LS3137 vs. TMS570LC4357: Flash bank width

Jiri Janacek
Genius 3315 points
Other Parts Discussed in Thread: TMS570LS3137, TMS570LC4357, HALCOGEN

Dear all,

I would like to ask you just for confirmation of the following statements defined within appropriate datasheets and TRMs of devices mentioned in the message title.

TMS570LS3137: bank 1-2 width == bank 7 width == 128 bits (+ 2 * 8 bits of ECC)

TMS570LC4357: bank 1-2 width == 256 bits (+ 4 * 8 bits of ECC); bank 7 width == 64 bits (+ 1 * 8 bits of ECC)

Right?

Well, let me focus on TMS570LS3137:

Obviously, dataI block passed via ATCM into the flash must not exceed 16 Bytes. I would expect and also have tested on HW (;-)) that narrower data block (8 Bytes wide) is passed through without any problems.

Anyway I have got unexpected results when the data block of 16 Bytes has been sent into EEPROM (bank 7) data has been stored in the weird shape. The data block of the same width sent into flash (bank 0 or bank 1) has been stored as expected.

We do not use EEPROM emulation layer provided by HalCoGen - maybe I should suspect our driver above the TI F021 low level library, should not?

So finally, my question - is the bank 7 (EEPROM) width of TMS570LS3137 really equal to 128 bits? I know that the TMS570LC4357 device has a bit different sector layout of the bank 7 in comparison to the device TMS570LS3137 but it seems that TMS570LS3137 also requires 64 bit limit ;-)

Thanks a lot in advance,

Best regards, Jiri

  • 0
    TI__Mastermind 49120 points
    Jiri,

    I will check with the flash API expert as to how the programming of the bank 7 is implemented. The bank 7 is also 144-bit wide (128 data bits + 16 ECC bits) in LS3137.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    TI__Mastermind 35865 points

    Hi Jiri,

    Bank 7 (EEPROM) width of TMS570LS3137 is 144 bits (128 data bits + 16 ECC bits) .

    You should be able to program 16 bytes in a single programming operation on bank7.

    However, the start address and the length cannot exceed the bank width. For e.g: Programming 14 bytes on a 16 byte wide bank starting at address 0x4 is not allowed.

    Please check your code and see if this is implemented correctly.

    Best Regards,

    Siddharth

  • 0 in reply to Siddharth Deshpande
    TI__Expert 6985 points

    Hi All,

    I'm not sure if it is relevant, but there are differences in how the flash is accessed in the TMS570LS3137 device and in the TMS570LC device:

    On the TMS570LS3137 the two main flash banks are connected to the CPU via the 64-Bit wide ATCM bus, the Bank 7 (EEPROM) or FWM (Flash Wrapper Module) Bus2 Interface (64-Bit) is connected via the 64-Bit wide SCR (Switched Central Resource) and the 64-Bit wide AXI master interface.

    We do know that there can be issues with accessing peripherals with burst access (DEVICE#B071), which I guess is the case if you do a 128-Bit write to a location in Bank 7 (EEPROM).

    So please check if you use burst accesses to the Bank 7 and how the MPU is setup for the Bank 7 address space. If it is setup as Normal type memory, the CPU's store buffer might merge consecutive writes to the Bank 7 address space, and thus issues bursts via the SCR. If either of these is the case this might result in "weird shaped" data stored to Bank 7.

    However, my guess is that 64-Bit access are ok as the complete data path between the CPU and the FWM is 64-Bit wide.

    On the TMS507LCx devices all Flash Banks are connected via the AXI Master interface of the Cortex-R5F CPU. On this device the most important thing is to get MPU configuration right for using the caches, when writing to a flash bank it should be at least configured as Write Through to ensure that writes to the flash bank are happening.

    On all devices it should also be possible to use the FWM register interface to write to the Flash Bank instead of writing directly to the Flash Bank.
    With this I mean using the Flash Wide Programming Write Data Registers as described in SPNA148, instead of pointing directly to the Flash address space for writing.

    Best Regards,
    Christian