a question about the EMIF_RnW signal

user4074391

Other Parts Discussed in Thread: TMS570LC4357, RM57L843

the EMIF_NWE signal wrong

i use the EMIF asyschronous (CS3), which start address is 0x64000000.

#define SHAR (0x64000000 + 0x08)
#define SHAR0 SHAR
#define SHAR1 (SHAR + 1)
#define SHAR2 (SHAR + 2)
#define SHAR3 (SHAR + 3)
#define SHAR4 (SHAR + 4)
#define SHAR5 (SHAR + 5)
void main(void)
{
/* USER CODE BEGIN (3) */
gioInit();
hetInit();
muxInit();
emif_SDRAMInit();
emif_ASYNC1Init();
emif_ASYNC2Init();
emif_ASYNC3Init();
IINCHIP_WRITE(SHAR, ((uint16)(mac[0]<<8)&0xFFFF)+(uint16)mac[1]); //(step1)
IINCHIP_WRITE(SHAR2,((uint16)(mac[2]<<8)&0xFFFF)+(uint16)mac[3]);//(step2)
IINCHIP_WRITE(SHAR4,((uint16)(mac[4]<<8)&0xFFFF)+(uint16)mac[5]);//(step3)
while(1);
}
void IINCHIP_WRITE(uint32 addr,uint16 data)
{

(*((vuint16*)addr)) = data;
}

when debug from step1 to step2, the EMIF_RnW(bule) and EMIF_CS3(green) signal is show inthe figure.
i think the EMIF_CS3 signal is right while the EMIF_RnW signal is wrong, because i only write once but there are
three write process. is that right?

over 10 years ago

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago

TI__Genius 11645 points

Hi,

Can you please let us know the device that you are trying this out.

This is a known issue listed in our errata document, please have a look at the errata list once based the device that you are seeing.

For ex : If you are using TMS570LC4357 - then please refer to errata DEVICE#39 from SPNZ180B

0 user4074391 over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Intellectual 410 points

i use TMS570LC4357, from the DEVICE#39 from SPNZ180B, i can not use the emif to write to and read from fifo memory devices, is that right?

0 user4074391 over 10 years ago in reply to user4074391

Intellectual 410 points

i need the EMIF to connect 16bit FIFO memory（CS3 CS4 ） and Dual Port RAM（CS2），the TMS570LC4357 and RM57L843 are not suit for read the FIFO memory， is that right？from the silicon errata of RM46X 、RM48X and TMS570LX3137 only the WE signal is abnormal， which can be modified with DQM signals through an OR gate, and can connect to fifo memory almost nornmally. while the OE signal is normal , which is different from TMS570LC4357 and RM57L843.can i say RM46X 、RM48X and TMS570LX3137 are suit for my design. thanks very much!

0 Sunil Oak over 10 years ago in reply to user4074391

TI__Mastermind 49120 points

If you use the RM46x, RM48x, 570LS31x, LS21x, LS12x or LS11x MCUs, you can work around the WE signal issue by configuring the external memory range as device-type or strongly-ordered type.

0 user4074391 over 10 years ago in reply to Sunil Oak

Intellectual 410 points

do you mean that the additional dummy write pulses only in the "normal" type，WE signal is normal by configuring the external memory range as device-type or strongly-ordered type， the process for TMS570LC4357 that The WE signal may be externally gated (OR gate) with the DQM signals to suppress the extra

WE pulses is not necesary， thanks very much。

0 Sunil Oak over 10 years ago in reply to user4074391

TI__Mastermind 49120 points

Yes, the additional nWE pulse is only seen when writing to external asynchronous memory configured to be of "normal" type. As the workaround in the errata document suggests, configure external memory as device type or as strongly-ordered type, and you will not see the extra pulse on the nWE/RnW signals during a single write. This is only true for the RM4x, LS31x LS21x, LS12x and LS11x MCUs.

0 user4074391 over 10 years ago in reply to Sunil Oak

Intellectual 410 points

THANKS!

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a question about the EMIF_RnW signal