Hercules RM48L952ZWT Flash and EMIF/SDRAM

Hi Tammy,

1. emif_SDRAMInit() is used to configure the EMIF for SDRAM. After init, you can read/write from/to SDRAM.

SDRAMInit();
unsigned short *Addr = (unsigned short *) Start_Address;
unsigned int Pattern = 0x12345678;
unsigned int NO_OF_WORDS = 0x1000;

while(No_Of_Words > 0)
{
#if defined (_TMS470_LITTLE) || defined(__little_endian__)
*Addr++ = (Pattern & 0x0000FFFF);
*Addr++ = (Pattern & 0xFFFF0000)>>16;
#else
*Addr++ = (Pattern & 0xFFFF0000)>>16;
*Addr++ = (Pattern & 0x0000FFFF);
#endif
No_Of_Words--;
}

}

2. The HalCoGen doesn't generate Flash read/write/erase functions. Please use bl_flash.c in bootloader (downloadable from TI website) as reference for flash operation.

Regards,
QJ

Hi QJ,

Thank you.

1. How do we know what the start address is of SDRAM over EMIF? Or is it 0x00000000 to max size of SDRAM to the EMIF RM48 component (so in software start at 0x00000000? right now, if we i.e., create variables, etc. it is using what is on the RM48 or does it automatically after we run emif_SDRAMInit() use this SDRAM if it runs out of RM48 RAM?. But now we added extra 2 MB tod SDRAM over EMIF, how do we access it at runtime?

2. do you have a link to the TI website where to find bl_flash.c thank you.

Hi Tammy,

1. The start address of EMIF_CS0  (for SDRAM) is 0x80000000. I will post my SDRAM test CCS project for your reference

2. www.ti.com/.../getliterature.tsp;fileType=zip

Regards,

QJ

Hi QJ, I have downloaded the zip file for SDRAM test, thank you. I have some questions, what is the difference between the 32BIT vs 8BIT vs 16BIt tests? Is it dependent on the type of SDRAM? Or can we run all the tests? Also, how do we know if tests passes or fails?

when we run with TEST_EMIF_MEMORY_32BIT(EMIF_CS0_ADDRMAP_START, NO_OF_WORDS, 0x12345678); the pattern in memory is 0x12341234 and not the pattern 0x12345678 (the top 16 bytes are written over and over but not the bottom 16 bytes)

we changed your main test code was

void EMIF_BSPTest(void)
{
unsigned int i=0;
unsigned short *SRAM_ptr = ( unsigned short *)0x80000000;

*SRAM_ptr = 0x1234;
 
i = TEST_EMIF_MEMORY_32BIT(EMIF_CS0_ADDRMAP_START, NO_OF_WORDS, 0x12345678);
//if (i == 0) {
// i = TEST_EMIF_MEMORY_16BIT(EMIF_CS0_ADDRMAP_START, NO_OF_WORDS, 0x12345678);
}

//if (i == 0) {
//i = TEST_EMIF_MEMORY_16BIT(EMIF_CS2_ADDRMAP_START, NO_OF_WORDS, 0x55AA66BB);
//}

}

Thank you again.

Hi QJ, 

Another update. With your test code if we try to write 0x12345678, it does not update the SDRAM unless we actually reset the board via the CCS debugger. then what is inSDRAM over and over is 0x12341234 and not 0x12345678.

In Code Composer, after an immediate write  via your test code the memory browser does not show memory updated and expression window (we breakpoint and single step) we cannot write to sdram. Thank you again and now your test code deos not work either each time. In HalCoGen (and pages 33 and 34 of datasheet), what is required for multiplexing of terminals to have access to SDRAM on Hercules RM48L952ZWT? Do Terminals for RTPDATA/EMIF_Addr and EXP_EMIF need to be connected also? Do you want me to zip up our halcogen to send you?  Thank you again.

Hi OJ,

Thank you so much for your help on this.  Please see below portion of our schematic that is related to the SDRAM.  We were missing a 10k pull-up on terminal D16, but it has been added.  As you can see, we removed the unused multiplex connection to  RTPDATA and EXP_EMIF.  We don't have RTP connector on our desgin.  Please let us know if you see any issues.  If you need any additional info, please let me know.

Thank you.

Derrick

3782.HalCoGen.zipHi QJ,

 Here is the HalCoGen Configuration for EMIF and SDRAM if this helps.  Thank you again.