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RM46 Selftest PBIST

Arne Friebel
Intellectual 360 points


Dear Sirs,

We have some questions regarding the self-test function of the RM46. We use the code which is generated by the HALOGEN 4.03 Version.  

In regard to our software certification procedure according DIN61508 we want to use the protocol of this chat to add in our TÜV Safety Documentation to clarify certain code fragments which are not well described in your manual.

Your comments would be used to get the TÜV release on TI libraries and the associated Software Code.

Source : errata_PBIST_4()

    /* ROM_init Setup using special reserved registers as part of errata fix */
    /* (Only to be used in this function) */
    *(volatile uint32_t *)0xFFFF0400U = 0x0000000AU;
    *(volatile uint32_t *)0xFFFF040CU = 0x0000EE0AU;

This leads to the FMTM Test Controller (in SPNU514A no other comment to FMTM and its registers)

            /* Load PBIST ALGO to initialize the ROMs */
            *(volatile uint32_t *)0xFFFFE400U = 0x00000001U;
            *(volatile uint32_t *)0xFFFFE440U = 0x00000025U;
            *(volatile uint32_t *)0xFFFFE404U = 0x62400001U;
            *(volatile uint32_t *)0xFFFFE444U = 0x00000004U;
            *(volatile uint32_t *)0xFFFFE408U = 0x00068003U;
            *(volatile uint32_t *)0xFFFFE448U = 0x00000000U;
            *(volatile uint32_t *)0xFFFFE40CU = 0x00000004U;
            *(volatile uint32_t *)0xFFFFE44CU = 0x00006860U;
            *(volatile uint32_t *)0xFFFFE410U = 0x00000000U;
            *(volatile uint32_t *)0xFFFFE450U = 0x00000001U;
            *(volatile uint32_t *)0xFFFFE540U = 0x000003E8U;
            *(volatile uint32_t *)0xFFFFE550U = 0x00000001U;
            *(volatile uint32_t *)0xFFFFE530U = 0x00000000U;

FFFF E400 is the start Address for the PBIST Controller. The following Register 000-15C are reserved.

  

         /* SELECT ROM */
            if (ROM_count == 1U)
               {
                /* SELECT PBIST ROM */
                *(volatile uint32_t *)0xFFFFE520U = 0x00000002U;
                *(volatile uint32_t *)0xFFFFE524U = 0x00000000U;
                pbistREG->RAMT                    = 0x01002008U;
               }
            else
               {
                /* SELECT STC ROM */
                *(volatile uint32_t *)0xFFFFE520U = 0xFFF0007CU;
                *(volatile uint32_t *)0xFFFFE524U = 0x0A63FFFFU;
                pbistREG->RAMT                    = 0x02002008U;
               }

1CC is the last documented Register


            /* Setup using special reserved registers as part of errata fix */
            /* (Only to be used in this function) */
            pbistREG->rsvd1[4U]    = 1U;
            pbistREG->rsvd1[0U]    = 3U;

            /* PBIST_RUN */
            pbistREG->rsvd1[1U]    = 1U;

In reg_pbist.h:

    uint32_t DLR;            /**< 0x0164: Datalogger Register                 */
    uint32_t rsvd1[6U];        /**< 0x0168 - 0x017C: Reserved                    */
    uint32_t PACT;            /**< 0x0180: PBIST Activate Register             */

            if ((pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 |
                 pbistREG->FSRDL1 | pbistREG->rsvd4[0U] | pbistREG->rsvd4[1U]) != 0U)

Why is here not FSRF0 or FSRF1 used for failure detection

    /* ROM restore default setup */
    /* (must be completed before continuing) */
    *(volatile uint32_t *)0xFFFF040CU = 0x0000AA0AU;
    *(volatile uint32_t *)0xFFFF040CU = 0x0000AA05U;
    *(volatile uint32_t *)0xFFFF0400U = 0x00000005U;

Unkown Register

Please comment the pmu setting within these function.

Please verify that all of the settings are correct and that no error exists for this function.

Why are these registers called as reserved and whats the reason for hiding them in the documentation.

Best Regards A. Friebel

  • 0
    TI__Guru**** 198766 points

    Hi Arne,

    This version silicon has a PBIST bug. It is possible that the PBIST algorithms will not be downloaded from ROM to PBIST RAM. The PBIST test may return a pass status (FSRF0) even though the algorithm was not properly executed. This is very the code uses FSRA0/1 (address) and FSRDL0/1(data) to check if there is a failure.

    The rsv1s are registers for TI internal use only. They are used only for the workaround for PBIST#4 bug. This bug will be fixed in next revision.

    PMU is the performance monitoring unit. The code execution time can then be calculated by multiplying the counted CPU clock cycles with the clock period.

    The PMU consists of four counters: one only counting clock cycles and three for counting selectable events. The errata_PBIST_4 function uses cycle counter to count the clock cycles.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 360 points

    Dear Mr. Wang,

    thanks for your Email.

    Please can you confirm that even with new silicon revisions the "old" pbist_errata4 function and the other "old" pbist functions will work properly.

    (So that we can freeze in the function at this time)

    Please can you confirm that all pbist functions in HALOGEN4.03.00 will be checked by TI seriously, so that even with that silicon bug the pbist function will work properly.

    Are the tests made with the MARCH13N Algorithms

    (The TÜV prefers this algorithms)

    Best regards A.Friebel

  • 0 in reply to Arne Friebel
    TI__Guru**** 198766 points
    Hi Arne,

    For certification, I recommend to use Hercules SafeTI Diagnostic Library which is a collection of software functions and response handlers for various safety features of the Hercules Safety MCUs. The library should be tested by TI seriously. The SL_SelfTest_PBIST(...) function accepts different algorithms .

    Regards,
    QJ