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HALCoGen 4.02 mibspi parity checks

Other Parts Discussed in Thread: TMS570LS3137

Hello,

In sys_selftest.c for the TMS570LS3137, the first few lines of mibspi1ParityCheck() are in a different order compared to mibspi3ParityCheck() and mibspi5ParityCheck().  Is there a functional reason for the different ordering, or can I make them all the same?

Thanks, Charlie Johnston

mibspi1ParityCheck():

    /* enable multi-buffered mode */
    mibspiREG1->MIBSPIE = 0x1U;

    /* enable parity error detection */
    mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0xAU);

    /* enable parity test mode */
    mibspiREG1->UERRCTRL |= 0x00000100U;

    /* flip bit 0 of the parity location */
    mibspiPARRAM1 ^= 0x1U;

    /* disable parity test mode */
    mibspiREG1->UERRCTRL &= 0xFFFFFEFFU;

mibspi3ParityCheck() and mibspi5ParityCheck():

    /* enable multi-buffered mode */
    mibspiREG3->MIBSPIE = 0x1U;

    /* enable parity test mode */
    mibspiREG3->UERRCTRL |= 0x00000100U;

    /* flip bit 0 of the parity location */
    mibspiPARRAM3 ^= 0x1U;

    /* enable parity error detection */
    mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0xAU);

    /* disable parity test mode */
    mibspiREG3->UERRCTRL &= 0xFFFFFEFFU;