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RM57 MibSPI TG interrupt settings

Yuncheng Song
Intellectual 320 points
Other Parts Discussed in Thread: HALCOGEN

Hi all,

There is really very limited documentation about MibSPI TG interrupt setup. I could not find an example for this purpose. 


1. How can I enable the system level interrupt?

2. How can I enable the MibSPI TG7 complete interrupt?

3. How can I link the TG7 complete interrupt to a ISR function?

It will be good to have an example of MibSPI interrupt. Thanks

Yuncheng

Some suggestions:

1. The technical reference for RM57x is really sub standard, there are numerous errors all over place.

2. In CCS 6.1 there is no way to restart the program as the restart button causing device disconnected.

3. The register name in technical reference does not match with the register name in CCS debug mode.

  • 0
    TI__Guru**** 199106 points
    Hi Yuncheng,

    I have forwarded your question to one of our experts. He will get back with you shortly.

    Regards,
    QJ
  • 0 in reply to QJ Wang
    Intellectual 320 points
    Thanks QJ.

    I partially found a workaround. For some reason, the low level interrupt trigger are routed to VIM in a way of high level interrupt channel. There is a hell of confusion between HalCoGen generated code, technical reference, and register names in CCS debug.
    I managed to have the TG complete interrupt worked. However, having this issue straight up will be beneficial to the user group.
  • 0 in reply to QJ Wang
    TI__Guru**** 191906 points

    Hello Yuncheng,

     1.  At the system level you need to make sure you enable the processor interrupt. You can call _enable_IRQ_interrupt_() to enable the IRQ interrupt. This function is defined in the HL_sys_core.asm. In addition, you need to enable the interrupt for the corresponding MibSPI module in the VIM module. The mapping is defined in Table 5-35 Interrupt Request Assignments in the RM57 Datasheet.  If you are using HalcoGen, you will find VIM Channel 0-31, VIM Channel 32-63,  VIM Channel 64-95 and VIM Channel 96-127 tabs. Select the interrupt for the MibSPI instance you are working with. If you are using MibsSPI1 you will go to the VIM Channel 0-31 tab to enable either channel 12 or 26 corresponding to MibSPI1 High and Low interrupts. For other MibSPIx, you can do the same. There is also API that you can use to enable different channels in the VIM. For example you can call  the vimEnableInterrupt(12, SYS_IRQ) to enable MibSPI1 High Interrupt. The vimEnableInterrupt() is defined in HL_sys_vim.h

     2. At the module level, to enable interrupt for TGx, you can use the API mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level). You just give the TG number and the priority level. The API is defined HL_mibSpi.h.

     3.  I will suggest that you take a look at the VIM RAM tab in HalCoGen. HalCoGen assigns default ISR names. For example, if you are using MibSPI1 high level interrupt the default ISR is called mibspi1HighLevelInterrupt(). The vector address of the ISR is copied to the VIM RAM during the startup of the device. See vimInit() in the HL_sys_vim.c.

      Also thank you for your feedback on the documentation improvements.

  • 0 in reply to Charles Tsai
    Intellectual 320 points
    Hi Charles,

    Thanks for your answer. I managed to have MibSPI TG interrupt working. Thanks again for your help.

    best,

    Yuncheng