Unreliable reset

Richard Bland

Expert 2050 points

Other Parts Discussed in Thread: TM4C123GH6PGE

Using a TM4C123GH6PGE and CCSv5.5

My code always starts correctly when using the debugger, but if I build a release version of my code and program it onto my target board it does not always start. Pressing the reset button on the board will often start it correctly. Powering up the board is the the same, sometimes it starts, sometimes not.

I have the properties set the same in both debug and release.

I'm fairly sure the code is getting stuck during peripheral setup. I have put a short delay after each SysCtlPeripheralEnable as discussed elsewhere on the forum.

Can anyone suggest anything else to look for please.

Thanks

Richard

over 10 years ago

0 Luis Afonso over 10 years ago

Guru 20670 points

Hi Richard, could you post your code? Have you checked for a fault ISR after a core reset? After pressing the reset button the registers keep the config so you may be missing something that at the first run gives an error due to wrong order setup or wrong timing (though you said you added the wait cycle) which after a reset is kept on allowing for a "correct setup"

0 Amit Ashara over 10 years ago

TI__Guru**** 244400 points

Hello Richard,

When the code does not start, you can connect the debugger without downloading the code, load the out file as a symbol file to see where the code is getting stuck. That will give some important info on what is happening during code execution.

Regards
Amit

0 Richard Bland over 10 years ago in reply to Amit Ashara

Expert 2050 points

Hi,

Thanks for your replies. My initialisation code file is below (I hope!)

Amit, I did not realise that I could connect the debugger without downloading the code. Could you tell me how to do that please, as I have only ever started the debugger with the debug button on the toolbar which automatically compiles and downloads the debug version of the code first.

Further in my investigations I have been toggling a pin at various places through the initialisation and watching on a 'scope to try to establish where it is getting stuck. This is Led0On and Led0Off in my code below. This changes the reset reliability and now with the pin changing at each peripheral init the code seems to reset reliably! What's going on?

Fullscreen initialise.c Download

#include "stdint.h"
#include "stdbool.h"

#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_uart.h"
#include "inc/hw_gpio.h"
#include "inc/hw_ssi.h"
#include "inc/tm4c123gh6pge.h"

#include "driverlib/rom.h"
#include "driverlib/uart.h"
#include "driverlib/adc.h"
#include "driverlib/timer.h"
#include "driverlib/gpio.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/ssi.h"
#include "driverlib/udma.h"

#include "main.h"
#include "madi.h"
#include "initialise.h"
#include "fpga.h"
#include "uart.h"
#include "dmiuart.h"
#include "dac.h"
#include "aes.h"
#include "optocore.h"
#include "hydra.h"

#define Led0On			ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, GPIO_PIN_0)
#define	Led0Off			ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0x00)

//.....................................................................................
int wait(void)	//used to ensure SysCtlPeripheralEnable() has enough time to complete
{
int i, j;
	Led0On;
	j = 0;
	for(i=0;i<5;i++)
		j++;
	Led0Off;
	return j;
}

//----------------------------------------------------------------------------------------------------
void initialiseHardware(void)
{

	//Set ForceBootloader Pin..........................................................................................
	int regVal;
	regVal = HWREG(0x400FE000 + 0x1D0);						//read BOOTCFG
	if(regVal & 0x00000100) {								//check EN bit - if set, program BOOTCFG
		HWREG(FLASH_CTRL_BASE + 0x00) = 0x75100000;				//FMA addr of BOOTCFG
		HWREG(FLASH_CTRL_BASE + 0x04) = 0x0000D812;				//FMD data PG6 pulled low, en=0, key=1 - dmi
		HWREG(FLASH_CTRL_BASE + 0x08) = 0xA4420008;				//FMC key | commit (key=1 in FMD)
		while((HWREG(FLASH_CTRL_BASE + 0x08)) & 0x00000008) ;	//poll for CMT bit to be clear (finished commit)
	}

  //MainClock...............................................................................................................................
    ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_25MHZ);    //clocking from PLL at 50MHz

    ROM_IntMasterDisable();				//disable interrupts master

  //PortN...............................................................................................................................
  	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPION);			//**test - initialise first in order to be able to use pin for diagnostics
  	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);			//pins 0,1 leds
  	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1);

  	//PortA...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOA);				//PortA
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);    		//pins 0 UART0 rx, 1 UART0 tx
	wait();
																//pins 2,3,4,5 SSI0

  //PortB...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOB);				//PortB
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);			//pins 0,1,2,3 fpga boot
	wait();
																//pins 4,5 SSI2
	ROM_GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_0);		//FDONE
	ROM_GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_1);		//INIT_B
	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_2);		//CCLK
	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_3);		//PROG_B

  //PortC...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOC);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);			//pins 4 UART1 rx, 5 UART 1 tx
	wait();

  //PortD...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOD);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);			//pins 0,1,2,3 SSI1
	wait();
	ROM_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_6);		//pins 4,5 uart 6, pin 6 master slave in orangebox, pin7 spare fpga

  //PortE...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOE);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);			//pins 0,1,2,3 fpga gpio TXREDY, RXREDY, RXSYNC, spare
	wait();
	ROM_GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_1);
	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_2);

  //PortF...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOF);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);			//pins 0..7 fpga data
	wait();
    HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = 0x4C4F434B;			//F0 is locked as NMI by default
    HWREG(GPIO_PORTF_BASE + GPIO_O_CR) = 0xFF;
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_0);
	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 );

  //PortG...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOG);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);			//pins 0..5 board id, pin 6 is force bootloader jumper
	wait();
	ROM_GPIOPinTypeGPIOInput(GPIO_PORTG_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6);

  //PortH...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOH);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);			//pins 6,7 SSI2
	wait();
//	ROM_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE, GPIO_PIN_6);		//FLASH_SO
//	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_7);		//FLASH_SI

  //PortJ...............................................................................................................................
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOJ);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);			//pins 0,1 UART 4
	wait();

  //PortK...............................................................................................................................
  //PortL...............................................................................................................................
  //PortM...............................................................................................................................
//  //PortN...............................................................................................................................
//	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPION);
//	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);			//pins 0,1 leds
//	wait();
//	ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0 | GPIO_PIN_1);

  //PortP...............................................................................................................................

  //UART0...............................................................................................................................
	ROM_GPIOPinConfigure(GPIO_PA0_U0RX);									//set up pins PA0 and PA1 for UART use
	ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
	ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UART0);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);    					//enable the UART peripheral and clock
	wait();

	ROM_UARTDisable(UART0_BASE);											//disable while we set it up

	ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);     // Set the default UART configuration.
	ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);		//set interrupt levels
	ROM_UARTFIFOEnable(UART0_BASE);											//enable hardware fifo
	ROM_UARTIntDisable(UART0_BASE, 0xFFFFFFFF);								//clear the mask reg
	ROM_UARTIntClear(UART0_BASE, ROM_UARTIntStatus(UART0_BASE, false));		//clear int flags
	ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);					//TX int on end of transmission
	ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);				//set mask reg to enable rx ints
//	ROM_IntEnable(INT_UART0);    											//enable interrupt

	ROM_UARTEnable(UART0_BASE);												//enable UART

  //UART1...................................................................//used on Optocore card only...............................
	ROM_GPIOPinConfigure(GPIO_PC4_U1RX);									//set up pins PC4 and PC5 for UART use
	ROM_GPIOPinConfigure(GPIO_PC5_U1TX);
	ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UART1);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);    					//enable the UART peripheral and clock
	wait();

	ROM_UARTDisable(UART1_BASE);											//disable while we set it up

	ROM_UARTConfigSetExpClk(UART1_BASE, ROM_SysCtlClockGet(), 57600, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);     // Set the default UART configuration.
	//UARTFlowControlSet(UART1_BASE, UART_FLOWCONTROL_NONE);				//uart1 can have hardware flow control
	ROM_UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);		//set interrupt levels
	ROM_UARTFIFOEnable(UART1_BASE);											//enable hardware fifo
	ROM_UARTIntDisable(UART1_BASE, 0xFFFFFFFF);								//clear the mask reg
	ROM_UARTIntClear(UART1_BASE, ROM_UARTIntStatus(UART1_BASE, false));		//clear int flags
	ROM_UARTTxIntModeSet(UART1_BASE, UART_TXINT_MODE_EOT);					//TX int on end of transmission
	ROM_UARTIntEnable(UART1_BASE, UART_INT_RX | UART_INT_RT);				//set mask reg to enable rx ints
//	ROM_IntEnable(INT_UART1);    											//enable interrupts now that the application is ready to start.

	ROM_UARTEnable(UART1_BASE);												//enable UART

  //UART4...................................................................//used on Hydra card only..................................
	ROM_GPIOPinConfigure(GPIO_PJ0_U4RX);									//set up pins PJ0 and PJ1 for UART use
	ROM_GPIOPinConfigure(GPIO_PJ1_U4TX);
	ROM_GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_0 | GPIO_PIN_1);
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UART4);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4);    					//enable the UART peripheral and clock
	wait();

	ROM_UARTDisable(UART4_BASE);											//disable while we set it up

	ROM_UARTConfigSetExpClk(UART4_BASE, ROM_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);     // Set the default UART configuration.
//	ROM_UARTFIFOLevelSet(UART4_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);		//set interrupt levels
//	ROM_UARTFIFOEnable(UART4_BASE);											//enable hardware fifo
	ROM_UARTIntDisable(UART4_BASE, 0xFFFFFFFF);								//clear the mask reg
	ROM_UARTIntClear(UART4_BASE, ROM_UARTIntStatus(UART4_BASE, false));		//clear int flags
	ROM_UARTTxIntModeSet(UART4_BASE, UART_TXINT_MODE_EOT);					//TX int on end of transmission
	ROM_UARTIntEnable(UART4_BASE, UART_INT_RX | UART_INT_RT);				//set mask reg to enable rx ints
//	ROM_IntEnable(INT_UART4);    											//enable interrupts now that the application is ready to start.

	ROM_UARTEnable(UART4_BASE);												//enable UART

  //UART6...................................................................//connects to other dmi card across backplane of blackbox.......
	ROM_GPIOPinConfigure(GPIO_PD4_U6RX);									//set up pins PD6 and PD7 for UART use
	ROM_GPIOPinConfigure(GPIO_PD5_U6TX);
	ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_4);
	ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_5);
//	ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_6);
//	HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = 0x4C4F434B;						//fuck knows why!
//	HWREG(GPIO_PORTD_BASE + GPIO_O_CR) = 0xFF;								//
//	ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_7);
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UART6);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART6);    					//enable the UART peripheral and clock
	wait();

	ROM_UARTDisable(UART6_BASE);											//disable while we set it up

	ROM_UARTConfigSetExpClk(UART6_BASE, ROM_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE);     // Set the default UART configuration.
	//ROM_UARTFIFOLevelSet(UART6_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);		//set interrupt levels
	//ROM_UARTFIFOEnable(UART6_BASE);											//enable hardware fifo
	ROM_UARTIntDisable(UART6_BASE, 0xFFFFFFFF);								//clear the mask reg
	ROM_UARTIntClear(UART6_BASE, ROM_UARTIntStatus(UART6_BASE, false));		//clear int flags
	ROM_UARTTxIntModeSet(UART6_BASE, UART_TXINT_MODE_EOT);					//TX int on end of transmission
	ROM_UARTIntEnable(UART6_BASE, UART_INT_RX | UART_INT_RT);				//set mask reg to enable rx ints
//	ROM_IntEnable(INT_UART2);    											//enable interrupts now that the application is ready to start.

	ROM_UARTEnable(UART6_BASE);												//enable UART

  //Timer0...............................................................................................................................
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);					//timer0 - scheduler ticker
	wait();
	ROM_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);

	ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, ROM_SysCtlClockGet() / 2000);	//set rate
	ROM_IntEnable(INT_TIMER0A);
	ROM_TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
	ROM_TimerEnable(TIMER0_BASE, TIMER_A);

  //SSI0..............................................................................................................................
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);			//fpga spi comms
	wait();
	ROM_SSIDisable(SSI0_BASE);									//disable it while we configure it
	ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
	ROM_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
	ROM_GPIOPinConfigure(GPIO_PA4_SSI0RX);
	ROM_GPIOPinConfigure(GPIO_PA5_SSI0TX);
	ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE,
					   GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2);	//tx, rx, fr, ck
	ROM_SSIClockSourceSet(SSI0_BASE,
						  SSI_CLOCK_SYSTEM);
	ROM_SSIConfigSetExpClk(SSI0_BASE,
						   ROM_SysCtlClockGet(),
						   SSI_FRF_TI,
						   SSI_MODE_MASTER,
						   5000000,
						   16);
	ROM_SSIEnable(SSI0_BASE);
	ROM_SSIDMAEnable(SSI0_BASE,
					 SSI_DMA_RX | SSI_DMA_TX);
//	ROM_IntEnable(INT_SSI0);    					//enable SSI0 peripheral interrupts, note that no interrupts were enabled, but the uDMA controller will cause an interrupt on the SSI0 interrupt signal when a uDMA transfer is complete

  //SSI1..............................................................................................................................
	//ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);			//fpga spi1
	//ROM_GPIOPinConfigure(GPIO_PD0_SSI1CLK);
	//ROM_GPIOPinConfigure(GPIO_PD1_SSI1FSS);
	//ROM_GPIOPinConfigure(GPIO_PD2_SSI1RX);
	//ROM_GPIOPinConfigure(GPIO_PD3_SSI1TX);
	//ROM_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
	//ROM_SSIConfigSetExpClk(SSI1_BASE, ROM_SysCtlClockGet(), SSI_FRF_TI, SSI_MODE_SLAVE, 25000000, 16);
	//ROM_SSIEnable(SSI1_BASE);

  //SSI2..............................................................................................................................
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);			//flash spi
	wait();
	ROM_SSIDisable(SSI2_BASE);									//disable it while we configure it
	ROM_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
	ROM_GPIOPinConfigure(GPIO_PB5_SSI2FSS);
	ROM_GPIOPinConfigure(GPIO_PH6_SSI2RX);
	ROM_GPIOPinConfigure(GPIO_PH7_SSI2TX);
	ROM_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5);
	ROM_GPIOPinTypeSSI(GPIO_PORTH_BASE, GPIO_PIN_6 | GPIO_PIN_7);
	ROM_SSIClockSourceSet(SSI2_BASE, SSI_CLOCK_SYSTEM);
	ROM_SSIConfigSetExpClk(SSI2_BASE, ROM_SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 4000000, 8);
	ROM_SSIEnable(SSI2_BASE);

  //uDMA..............................................................................................................................
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
	wait();
	ROM_uDMAEnable();    								// Enable the uDMA controller.
	ROM_uDMAControlBaseSet(uDmaControlTable);    		// Point at the control table to use for channel control structures.

	//rx
	ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0RX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);    // Put the attributes in a known state for the uDMA SSI0RX channel.  These should already be disabled by default.
	ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
							  UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4);   	// Configure the control parameters for the primary control structure for the SSI RX channel.
	ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI0RX | UDMA_ALT_SELECT,
							  UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4);   	// Configure the control parameters for the alternate control structure for the SSI RX channel.
	ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
							   UDMA_MODE_PINGPONG,
							   (void *)(SSI0_BASE + SSI_O_DR),
							   SSIRXbufA,
							   SSI_RXBUF_SIZE);   												// Set up the transfer parameters for the SSI RX primary control structure.
	ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_ALT_SELECT,
							   UDMA_MODE_PINGPONG,
							   (void *)(SSI0_BASE + SSI_O_DR),
							   SSIRXbufB,
							   SSI_RXBUF_SIZE);   												// Set up the transfer parameters for the SSI RX alternate control structure.
//	ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI0RX);

	//tx
	ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0TX,
									UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK | UDMA_ATTR_USEBURST);    // Put the attributes in a known state for the uDMA SSI0TX channel.  These should already be disabled by default.
	ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
							  UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_4);    	// Configure the control parameters for the SSI TX.  The uDMA SSI TX channel is used to transfer a block of data from a buffer to the SSI.
	ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
							   UDMA_MODE_BASIC,
							   SSITXnul,
							   (void *)(SSI0_BASE + SSI_O_DR),
							   SSI_TXNUL_SIZE);    												// Set up the transfer parameters for the uDMA UART TX channel.  This will configure the transfer source and destination and the transfer size.

//	ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI0TX);

  //ADC1...............................................................................................................................
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
	wait();
	//need to discard first 2 or 3 samples of temp sensor - see errata
    ROM_ADCSequenceDisable(ADC1_BASE, 2);    												//disable sequence before we change it
    ROM_ADCSequenceConfigure(ADC1_BASE, 2, ADC_TRIGGER_PROCESSOR, 0);    					//select processor (software) trigger
    ROM_ADCSequenceStepConfigure(ADC1_BASE, 2, 0, ADC_CTL_TS);  							//
    ROM_ADCSequenceStepConfigure(ADC1_BASE, 2, 1, ADC_CTL_TS);  							//
    ROM_ADCSequenceStepConfigure(ADC1_BASE, 2, 2, ADC_CTL_TS);  							//
    ROM_ADCSequenceStepConfigure(ADC1_BASE, 2, 3, ADC_CTL_TS | ADC_CTL_IE | ADC_CTL_END);	//
    ROM_ADCIntClear(ADC1_BASE, 2);    														//clear the interrupt status flag
    ROM_ADCSequenceEnable(ADC1_BASE, 2);    												//enable sequence

  //...............................................................................................................................
	ROM_IntMasterEnable();					//enable interrupts master


//	ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, GPIO_PIN_0);	//led 0 on
}

//------------------------------------------------------------------
void initialiseSoftware(void)
{
	//...........................read ids.............................................
	card_type = read_CARD_TYPE;
	card_type += 20;				//add base id

	if(read_MASTER == 0)		//read orangebox master/slave pin
		orange_master = 1;		//card is in the master slot of an orange box
	else
		orange_master = 0;		//card is either in a spitfire engine or in the slave slot of an orange box

	orange_slave = 0;			//initialise - can be set by message received from other card

	//...........................start fpga comms.............................................
	initSSI();					//serial comms with fpga

	if(FPGAbooted) {
		RXSYNC_HI;				//reset rx sync in fpga
		RXSYNC_LO;

		ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI0RX);		//enable SSI comms with fpga
		ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI0TX);

		ROM_IntEnable(INT_SSI0);	//this essential to start after UDMA
	}

	//...............................start uarts........................................
	ROM_IntEnable(INT_UART0);		//uart to spitfire engine
    ROM_UARTCharPut(UART0_BASE, 33);		//TODO this seems to kick start the tx comms

    ROM_IntEnable(INT_UART4);		//uart to Hydra module
    ROM_UARTCharPut(UART4_BASE, 33);		//TODO this seems to kick start the tx comms

    ROM_IntEnable(INT_UART6);		//uart to other card in Orange Box
    ROM_UARTCharPut(UART6_BASE, 33);		//TODO this seems to kick start the tx comms

	setSyncMode(0x0000);	//all cards sync to DMI by default
	//stand-alone testing only......................................................
	//setSyncMode(1);		//enable internal 48K clock
	//setSyncMode(4);		//loopback audio

	switch(card_type) {
	case 20:			//DMI BNC MADI card
		initialise_MADI();
		break;
	case 21:			//DMI A/D card
		//initialise_ADC();
		break;
	case 22:			//DMI D/A card
		initialise_DAC();
		break;
	case 23:			//DMI AES card
		initialise_AES();
		break;
	case 24:			//DMI CAT5 MADI card
		initialise_MADI();
		break;
	case 25:			//DMI WAVES card
//		initialise_WAVES();
		break;
	case 26:			//DMI AVIOM card
//		initialise_AVIOM();
		break;
	case 27:			//DMI DANTE card
//		initialise_DANTE();
		break;
	case 28:			//DMI OPTOCORE card
		initialise_OPTOCORE();
		break;
	case 29:			//DMI HYDRA card
		initialise_HYDRA();
		break;
	}

	if(orange_master == 1) {
		set_orange_master_defaults();
	}
}

0 Amit Ashara over 10 years ago in reply to Richard Bland

TI__Guru**** 244400 points

Hello Richard,

In CCS, go to View -> Target Configurations. This will open a new tab. Go to user defined, right click -> New Target Configuration. Give it a name and assign the debugger property of the debugger being used, target device, etc. The Right Click the Configuration-> Launch Selected Configuration. Once done, right click the core and select Connect target. From this point on it will work as a connect w/o download. You can then load the out file as a symbol file.

By the description of the what you mentioned and the code, I would suggest making a change in the code as below

Enable Periph A
Configure Periph A
Enable Periph B
Configure Periph B

to

Enable Periph A
Enable Periph B
Configure Periph A
Configure Periph B

or
Enable Periph A
while(!(SysCtlPeripheralReady(A)));
Configure Periph A

Regards
Amit

0 Richard Bland over 10 years ago in reply to Amit Ashara

Expert 2050 points

Dear Amit,
I was not aware of the SysCtlPeripheralReady() function! This has sorted out my issues. I am very grateful to you for your help here, it has been driving me mad! It is also useful to understand a bit more about Target Configurations in CCS.
Many thanks.
Richard

0 Amit Ashara over 10 years ago in reply to Richard Bland

TI__Guru**** 244400 points

Hello Richard,

All examples going forward are going to have the check. Once forward looking designs get the update, then we go back to TovaWare designs examples

Regards
Amit

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