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Possible erros in uDMA UART example

Bruno Saraiva
Guru 13040 points
Other Parts Discussed in Thread: EK-TM4C1294XL

Hi all,

I'm trying to program a proper uDMA UART receive and transmit firmware, coming from the uDMA example:

// udma_demo.c - uDMA example.

// This is part of revision 2.1.0.12573 of the EK-TM4C1294XL Firmware Package.

Three points that caused me doubts:

1) Looking at the line

ROM_UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

and at the comment below, right before the uDMA control set:

//  The arbitration size is set to 4 to match the RX FIFO trigger threshold.

ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
UDMA_ARB_4);

I would expect that FIFO_TX4_8 means 4/8 of 16bytes, which is 8 bytes. So is that control set REALLY matching FIFO to arbitration? I can see that the program works, but assuming examples have such an importance as a learning platform, that seems confusing and misleading (or am I still confused will all the uDMA parameters???)

2) There's a line (579) which is

    ROM_UARTIntEnable(UART1_BASE, UART_INT_DMATX | UART_INT_DMATX);

Again, program works as is, or after changing one of the same or'ed parameters to UART_INT_DMARX. Would RX be the correct setting?

3) Curiosity: I just noted that all my programs so far lack the enabling UARTEnable(UART1_BASE); And I have a lot of boards using lots of uarts! Is that set on by default, or have my programs been working by magic?

Happy Easter everyone!

  • 0
    TI__Guru**** 244400 points
    Hello Bruno,

    The uDMA works in two modes: Single Request and Burst Request. When enabled a peripheral asserts single request, it will transfer one unit of data. When Burst request is asserted by the peripheral the burst request in invoked where the ARB Size comes into picture. In uDMA can be configured to not accept Single request but only respond to burst request forcing ARB Size.

    In this particular case the Single Request is being asserted by UART and thus causing the transfer to occur one data unit at a time and hence it is working fine.

    You can check the peripheral register to see if the UARTEN, INTDMARX and INTDMATX bit is set or not. When run with a debugger and a CPU reset is done, the peripherals are not reset and hence an older setting may still prevail. Unless a system reset is done the older settings may continue.

    Regards
    Amit
  • 0
    Guru 20670 points
    1)Well the FIFO is definitely triggering when it has 8 values saved in it. Hum doesn't seem like the DMA empties the FIFO all the way. But... this uses ping-pong mode. Hum, even so each ping or pong would just empty 4 bytes. The 2nd transfer ("pong") should only transfer if the FIFO reaches 4/8 again so there's always 4 unread bytes in the FIFO.


    2)wat? :0
    1 of them should be UART_INT_DMARX if you want an interrupt when the DMA is done from taking data out of the Receive FIFO.


    3) UARTStdioConfig(0, 115200, g_ui32SysClock); takes care of that. Check the source files. Though this example does enable the UART


    Amit, could you confirm that ROM_UARTIntEnable(UART1_BASE, UART_INT_DMATX | UART_INT_DMATX); is wrong? Though the code should not work if the DMARX interrupt isn't enabled.
    Also the 1) seems like a mistake.
  • 0 in reply to Luis Afonso
    TI__Guru**** 244400 points
    Hello Luis,

    No it is not wrong. The interrupt for DMADONE for DMATX and RX is being enabled so that when the appropriate DMADONE triggers, the CPU gets notified.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 20670 points
    yes, correct that what should be happening but instead the DMATX is repeated twice instead of having DMATX and DMARX. (am I'm being blind?)
    The example in my tivaware package has the same error
  • 0 in reply to Luis Afonso
    TI__Guru**** 244400 points
    Hello Luis

    Sure, I can check that on my side, but doubtful that could be the issue.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 13040 points

    Amit,

    About the Burst/Single request, I understand now why the program is working even with arbitration set to 4.

    My point is that these examples are mostly used as a learning platform, created by Texas to teach their clients how to use their products. And the explanation that I mentioned ("//  The arbitration size is set to 4 to match the RX FIFO trigger threshold") misleads the comprehension, and in fact teaches a wrong concept (at least as far as I humbly understood it).

    About the TX/RX INT enable, Luis correctly pointed out: there seems to be a typo in the TivaWare example, as both parameters are written UART_INT_DMATX in line 579.

    Cheers

  • 0 in reply to Bruno Saraiva
    TI__Guru**** 244400 points
    Hello Bruno,

    Yes, you and Luis are correct. First of all there is an issue with the example. Also the comments at some places may be an oversight and be misleading.

    Regards
    Amit